Commit 30d53abd authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: Add AP807-quad cache description 



Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.

Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent 760cabcd

arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi

+42 −0
Original line number Diff line number Diff line
@@ -22,6 +22,13 @@ 
			enable-method = "psci";

			#cooling-cells = <2>;

			clocks = <&cpu_clk 0>;

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_0>;

		};

		cpu1: cpu@1 {

			device_type = "cpu";
@@ -30,6 +37,13 @@ 
			enable-method = "psci";

			#cooling-cells = <2>;

			clocks = <&cpu_clk 0>;

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_0>;

		};

		cpu2: cpu@100 {

			device_type = "cpu";
@@ -38,6 +52,13 @@ 
			enable-method = "psci";

			#cooling-cells = <2>;

			clocks = <&cpu_clk 1>;

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

		};

		cpu3: cpu@101 {

			device_type = "cpu";
@@ -46,6 +67,27 @@ 
			enable-method = "psci";

			#cooling-cells = <2>;

			clocks = <&cpu_clk 1>;

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

		};



		l2_0: l2-cache0 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

		};



		l2_1: l2-cache1 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

		};

	};

};

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