Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/bwh/sfc-next (30129cf2) · Commits · 戴 / test

drivers/net/ethernet/sfc/efx.c

+225 −43

Original line number	Diff line number	Diff line
		@@ -21,7 +21,9 @@
		#include <linux/ethtool.h>
		#include <linux/topology.h>
		#include <linux/gfp.h>
		#include <linux/pci.h>
		#include <linux/cpu_rmap.h>
		#include <linux/aer.h>
		#include "net_driver.h"
		#include "efx.h"
		#include "nic.h"
		@@ -73,7 +75,9 @@ const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
		const char *const efx_reset_type_names[] = {
		[RESET_TYPE_INVISIBLE] = "INVISIBLE",
		[RESET_TYPE_ALL] = "ALL",
		[RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
		[RESET_TYPE_WORLD] = "WORLD",
		[RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
		[RESET_TYPE_DISABLE] = "DISABLE",
		[RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
		[RESET_TYPE_INT_ERROR] = "INT_ERROR",
		@@ -84,8 +88,6 @@ const char *const efx_reset_type_names[] = {
		[RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
		};

		#define EFX_MAX_MTU (9 * 1024)

		/* Reset workqueue. If any NIC has a hardware failure then a reset will be
		* queued onto this work queue. This is not a per-nic work queue, because
		* efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
		@@ -117,9 +119,12 @@ MODULE_PARM_DESC(separate_tx_channels,
		static int napi_weight = 64;

		/* This is the time (in jiffies) between invocations of the hardware
		* monitor. On Falcon-based NICs, this will:
		* monitor.
		* On Falcon-based NICs, this will:
		* - Check the on-board hardware monitor;
		* - Poll the link state and reconfigure the hardware as necessary.
		* On Siena-based NICs for power systems with EEH support, this will give EEH a
		* chance to start.
		*/
		static unsigned int efx_monitor_interval = 1 * HZ;

		@@ -203,13 +208,14 @@ static void efx_stop_all(struct efx_nic *efx);
		#define EFX_ASSERT_RESET_SERIALISED(efx) \
		do { \
		if ((efx->state == STATE_READY) \|\| \
		(efx->state == STATE_RECOVERY) \|\| \
		(efx->state == STATE_DISABLED)) \
		ASSERT_RTNL(); \
		} while (0)

		static int efx_check_disabled(struct efx_nic *efx)
		{
		if (efx->state == STATE_DISABLED) {
		if (efx->state == STATE_DISABLED \|\| efx->state == STATE_RECOVERY) {
		netif_err(efx, drv, efx->net_dev,
		"device is disabled due to earlier errors\n");
		return -EIO;
		@@ -242,16 +248,10 @@ static int efx_process_channel(struct efx_channel *channel, int budget)
		struct efx_rx_queue *rx_queue =
		efx_channel_get_rx_queue(channel);

		/* Deliver last RX packet. */
		if (channel->rx_pkt) {
		__efx_rx_packet(channel, channel->rx_pkt);
		channel->rx_pkt = NULL;
		}
		if (rx_queue->enabled) {
		efx_rx_strategy(channel);
		efx_rx_flush_packet(channel);
		if (rx_queue->enabled)
		efx_fast_push_rx_descriptors(rx_queue);
		}
		}

		return spent;
		}
		@@ -625,20 +625,51 @@ fail:
		*/
		static void efx_start_datapath(struct efx_nic *efx)
		{
		bool old_rx_scatter = efx->rx_scatter;
		struct efx_tx_queue *tx_queue;
		struct efx_rx_queue *rx_queue;
		struct efx_channel *channel;
		size_t rx_buf_len;

		/* Calculate the rx buffer allocation parameters required to
		* support the current MTU, including padding for header
		* alignment and overruns.
		*/
		efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
		efx->rx_dma_len = (efx->type->rx_buffer_hash_size +
		EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
		efx->type->rx_buffer_hash_size +
		efx->type->rx_buffer_padding);
		efx->rx_buffer_order = get_order(efx->rx_buffer_len +
		sizeof(struct efx_rx_page_state));
		rx_buf_len = (sizeof(struct efx_rx_page_state) +
		EFX_PAGE_IP_ALIGN + efx->rx_dma_len);
		if (rx_buf_len <= PAGE_SIZE) {
		efx->rx_scatter = false;
		efx->rx_buffer_order = 0;
		} else if (efx->type->can_rx_scatter) {
		BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
		EFX_PAGE_IP_ALIGN + EFX_RX_USR_BUF_SIZE >
		PAGE_SIZE / 2);
		efx->rx_scatter = true;
		efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
		efx->rx_buffer_order = 0;
		} else {
		efx->rx_scatter = false;
		efx->rx_buffer_order = get_order(rx_buf_len);
		}

		efx_rx_config_page_split(efx);
		if (efx->rx_buffer_order)
		netif_dbg(efx, drv, efx->net_dev,
		"RX buf len=%u; page order=%u batch=%u\n",
		efx->rx_dma_len, efx->rx_buffer_order,
		efx->rx_pages_per_batch);
		else
		netif_dbg(efx, drv, efx->net_dev,
		"RX buf len=%u step=%u bpp=%u; page batch=%u\n",
		efx->rx_dma_len, efx->rx_page_buf_step,
		efx->rx_bufs_per_page, efx->rx_pages_per_batch);

		/* RX filters also have scatter-enabled flags */
		if (efx->rx_scatter != old_rx_scatter)
		efx_filter_update_rx_scatter(efx);

		/* We must keep at least one descriptor in a TX ring empty.
		* We could avoid this when the queue size does not exactly
		@@ -655,16 +686,12 @@ static void efx_start_datapath(struct efx_nic *efx)
		efx_for_each_channel_tx_queue(tx_queue, channel)
		efx_init_tx_queue(tx_queue);

		/* The rx buffer allocation strategy is MTU dependent */
		efx_rx_strategy(channel);

		efx_for_each_channel_rx_queue(rx_queue, channel) {
		efx_init_rx_queue(rx_queue);
		efx_nic_generate_fill_event(rx_queue);
		}

		WARN_ON(channel->rx_pkt != NULL);
		efx_rx_strategy(channel);
		WARN_ON(channel->rx_pkt_n_frags);
		}

		if (netif_device_present(efx->net_dev))
		@@ -683,7 +710,7 @@ static void efx_stop_datapath(struct efx_nic *efx)
		BUG_ON(efx->port_enabled);

		/* Only perform flush if dma is enabled */
		if (dev->is_busmaster) {
		if (dev->is_busmaster && efx->state != STATE_RECOVERY) {
		rc = efx_nic_flush_queues(efx);

		if (rc && EFX_WORKAROUND_7803(efx)) {
		@@ -1596,13 +1623,15 @@ static void efx_start_all(struct efx_nic *efx)
		efx_start_port(efx);
		efx_start_datapath(efx);

		/* Start the hardware monitor if there is one. Otherwise (we're link
		* event driven), we have to poll the PHY because after an event queue
		* flush, we could have a missed a link state change */
		if (efx->type->monitor != NULL) {
		/* Start the hardware monitor if there is one */
		if (efx->type->monitor != NULL)
		queue_delayed_work(efx->workqueue, &efx->monitor_work,
		efx_monitor_interval);
		} else {

		/* If link state detection is normally event-driven, we have
		* to poll now because we could have missed a change
		*/
		if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
		mutex_lock(&efx->mac_lock);
		if (efx->phy_op->poll(efx))
		efx_link_status_changed(efx);
		@@ -2309,7 +2338,9 @@ int efx_reset(struct efx_nic *efx, enum reset_type method)

		out:
		/* Leave device stopped if necessary */
		disabled = rc \|\| method == RESET_TYPE_DISABLE;
		disabled = rc \|\|
		method == RESET_TYPE_DISABLE \|\|
		method == RESET_TYPE_RECOVER_OR_DISABLE;
		rc2 = efx_reset_up(efx, method, !disabled);
		if (rc2) {
		disabled = true;
		@@ -2328,13 +2359,48 @@ out:
		return rc;
		}

		/* Try recovery mechanisms.
		* For now only EEH is supported.
		* Returns 0 if the recovery mechanisms are unsuccessful.
		* Returns a non-zero value otherwise.
		*/
		static int efx_try_recovery(struct efx_nic *efx)
		{
		#ifdef CONFIG_EEH
		/* A PCI error can occur and not be seen by EEH because nothing
		* happens on the PCI bus. In this case the driver may fail and
		* schedule a 'recover or reset', leading to this recovery handler.
		* Manually call the eeh failure check function.
		*/
		struct eeh_dev *eehdev =
		of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));

		if (eeh_dev_check_failure(eehdev)) {
		/* The EEH mechanisms will handle the error and reset the
		* device if necessary.
		*/
		return 1;
		}
		#endif
		return 0;
		}

		/* The worker thread exists so that code that cannot sleep can
		* schedule a reset for later.
		*/
		static void efx_reset_work(struct work_struct *data)
		{
		struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
		unsigned long pending = ACCESS_ONCE(efx->reset_pending);
		unsigned long pending;
		enum reset_type method;

		pending = ACCESS_ONCE(efx->reset_pending);
		method = fls(pending) - 1;

		if ((method == RESET_TYPE_RECOVER_OR_DISABLE \|\|
		method == RESET_TYPE_RECOVER_OR_ALL) &&
		efx_try_recovery(efx))
		return;

		if (!pending)
		return;
		@@ -2346,7 +2412,7 @@ static void efx_reset_work(struct work_struct *data)
		* it cannot change again.
		*/
		if (efx->state == STATE_READY)
		(void)efx_reset(efx, fls(pending) - 1);
		(void)efx_reset(efx, method);

		rtnl_unlock();
		}
		@@ -2355,11 +2421,20 @@ void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
		{
		enum reset_type method;

		if (efx->state == STATE_RECOVERY) {
		netif_dbg(efx, drv, efx->net_dev,
		"recovering: skip scheduling %s reset\n",
		RESET_TYPE(type));
		return;
		}

		switch (type) {
		case RESET_TYPE_INVISIBLE:
		case RESET_TYPE_ALL:
		case RESET_TYPE_RECOVER_OR_ALL:
		case RESET_TYPE_WORLD:
		case RESET_TYPE_DISABLE:
		case RESET_TYPE_RECOVER_OR_DISABLE:
		method = type;
		netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
		RESET_TYPE(method));
		@@ -2569,6 +2644,8 @@ static void efx_pci_remove(struct pci_dev *pci_dev)
		efx_fini_struct(efx);
		pci_set_drvdata(pci_dev, NULL);
		free_netdev(efx->net_dev);

		pci_disable_pcie_error_reporting(pci_dev);
		};

		/* NIC VPD information
		@@ -2741,6 +2818,11 @@ static int efx_pci_probe(struct pci_dev *pci_dev,
		netif_warn(efx, probe, efx->net_dev,
		"failed to create MTDs (%d)\n", rc);

		rc = pci_enable_pcie_error_reporting(pci_dev);
		if (rc && rc != -EINVAL)
		netif_warn(efx, probe, efx->net_dev,
		"pci_enable_pcie_error_reporting failed (%d)\n", rc);

		return 0;

		fail4:
		@@ -2865,12 +2947,112 @@ static const struct dev_pm_ops efx_pm_ops = {
		.restore = efx_pm_resume,
		};

		/* A PCI error affecting this device was detected.
		* At this point MMIO and DMA may be disabled.
		* Stop the software path and request a slot reset.
		*/
		pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
		enum pci_channel_state state)
		{
		pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
		struct efx_nic *efx = pci_get_drvdata(pdev);

		if (state == pci_channel_io_perm_failure)
		return PCI_ERS_RESULT_DISCONNECT;

		rtnl_lock();

		if (efx->state != STATE_DISABLED) {
		efx->state = STATE_RECOVERY;
		efx->reset_pending = 0;

		efx_device_detach_sync(efx);

		efx_stop_all(efx);
		efx_stop_interrupts(efx, false);

		status = PCI_ERS_RESULT_NEED_RESET;
		} else {
		/* If the interface is disabled we don't want to do anything
		* with it.
		*/
		status = PCI_ERS_RESULT_RECOVERED;
		}

		rtnl_unlock();

		pci_disable_device(pdev);

		return status;
		}

		/* Fake a successfull reset, which will be performed later in efx_io_resume. */
		pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
		{
		struct efx_nic *efx = pci_get_drvdata(pdev);
		pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
		int rc;

		if (pci_enable_device(pdev)) {
		netif_err(efx, hw, efx->net_dev,
		"Cannot re-enable PCI device after reset.\n");
		status = PCI_ERS_RESULT_DISCONNECT;
		}

		rc = pci_cleanup_aer_uncorrect_error_status(pdev);
		if (rc) {
		netif_err(efx, hw, efx->net_dev,
		"pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
		/* Non-fatal error. Continue. */
		}

		return status;
		}

		/* Perform the actual reset and resume I/O operations. */
		static void efx_io_resume(struct pci_dev *pdev)
		{
		struct efx_nic *efx = pci_get_drvdata(pdev);
		int rc;

		rtnl_lock();

		if (efx->state == STATE_DISABLED)
		goto out;

		rc = efx_reset(efx, RESET_TYPE_ALL);
		if (rc) {
		netif_err(efx, hw, efx->net_dev,
		"efx_reset failed after PCI error (%d)\n", rc);
		} else {
		efx->state = STATE_READY;
		netif_dbg(efx, hw, efx->net_dev,
		"Done resetting and resuming IO after PCI error.\n");
		}

		out:
		rtnl_unlock();
		}

		/* For simplicity and reliability, we always require a slot reset and try to
		* reset the hardware when a pci error affecting the device is detected.
		* We leave both the link_reset and mmio_enabled callback unimplemented:
		* with our request for slot reset the mmio_enabled callback will never be
		* called, and the link_reset callback is not used by AER or EEH mechanisms.
		*/
		static struct pci_error_handlers efx_err_handlers = {
		.error_detected = efx_io_error_detected,
		.slot_reset = efx_io_slot_reset,
		.resume = efx_io_resume,
		};

		static struct pci_driver efx_pci_driver = {
		.name = KBUILD_MODNAME,
		.id_table = efx_pci_table,
		.probe = efx_pci_probe,
		.remove = efx_pci_remove,
		.driver.pm = &efx_pm_ops,
		.err_handler = &efx_err_handlers,
		};

		/**************************************************************************

drivers/net/ethernet/sfc/efx.h

+12 −6

Original line number	Diff line number	Diff line
		@@ -33,17 +33,22 @@ extern int efx_setup_tc(struct net_device *net_dev, u8 num_tc);
		extern unsigned int efx_tx_max_skb_descs(struct efx_nic *efx);

		/* RX */
		extern void efx_rx_config_page_split(struct efx_nic *efx);
		extern int efx_probe_rx_queue(struct efx_rx_queue *rx_queue);
		extern void efx_remove_rx_queue(struct efx_rx_queue *rx_queue);
		extern void efx_init_rx_queue(struct efx_rx_queue *rx_queue);
		extern void efx_fini_rx_queue(struct efx_rx_queue *rx_queue);
		extern void efx_rx_strategy(struct efx_channel *channel);
		extern void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue);
		extern void efx_rx_slow_fill(unsigned long context);
		extern void __efx_rx_packet(struct efx_channel *channel,
		struct efx_rx_buffer *rx_buf);
		extern void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
		extern void __efx_rx_packet(struct efx_channel *channel);
		extern void efx_rx_packet(struct efx_rx_queue *rx_queue,
		unsigned int index, unsigned int n_frags,
		unsigned int len, u16 flags);
		static inline void efx_rx_flush_packet(struct efx_channel *channel)
		{
		if (channel->rx_pkt_n_frags)
		__efx_rx_packet(channel);
		}
		extern void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue);

		#define EFX_MAX_DMAQ_SIZE 4096UL
		@@ -67,6 +72,7 @@ extern void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue);
		extern int efx_probe_filters(struct efx_nic *efx);
		extern void efx_restore_filters(struct efx_nic *efx);
		extern void efx_remove_filters(struct efx_nic *efx);
		extern void efx_filter_update_rx_scatter(struct efx_nic *efx);
		extern s32 efx_filter_insert_filter(struct efx_nic *efx,
		struct efx_filter_spec *spec,
		bool replace);
		@@ -171,9 +177,9 @@ static inline void efx_device_detach_sync(struct efx_nic *efx)
		* TX scheduler is stopped when we're done and before
		* netif_device_present() becomes false.
		*/
		netif_tx_lock(dev);
		netif_tx_lock_bh(dev);
		netif_device_detach(dev);
		netif_tx_unlock(dev);
		netif_tx_unlock_bh(dev);
		}

		#endif /* EFX_EFX_H */

drivers/net/ethernet/sfc/enum.h

+9 −3

Original line number	Diff line number	Diff line
		@@ -137,8 +137,12 @@ enum efx_loopback_mode {
		* Reset methods are numbered in order of increasing scope.
		*
		* @RESET_TYPE_INVISIBLE: Reset datapath and MAC (Falcon only)
		* @RESET_TYPE_RECOVER_OR_ALL: Try to recover. Apply RESET_TYPE_ALL
		* if unsuccessful.
		* @RESET_TYPE_ALL: Reset datapath, MAC and PHY
		* @RESET_TYPE_WORLD: Reset as much as possible
		* @RESET_TYPE_RECOVER_OR_DISABLE: Try to recover. Apply RESET_TYPE_DISABLE if
		* unsuccessful.
		* @RESET_TYPE_DISABLE: Reset datapath, MAC and PHY; leave NIC disabled
		* @RESET_TYPE_TX_WATCHDOG: reset due to TX watchdog
		* @RESET_TYPE_INT_ERROR: reset due to internal error
		@@ -150,9 +154,11 @@ enum efx_loopback_mode {
		*/
		enum reset_type {
		RESET_TYPE_INVISIBLE = 0,
		RESET_TYPE_ALL = 1,
		RESET_TYPE_WORLD = 2,
		RESET_TYPE_DISABLE = 3,
		RESET_TYPE_RECOVER_OR_ALL = 1,
		RESET_TYPE_ALL = 2,
		RESET_TYPE_WORLD = 3,
		RESET_TYPE_RECOVER_OR_DISABLE = 4,
		RESET_TYPE_DISABLE = 5,
		RESET_TYPE_MAX_METHOD,
		RESET_TYPE_TX_WATCHDOG,
		RESET_TYPE_INT_ERROR,

drivers/net/ethernet/sfc/ethtool.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -154,6 +154,7 @@ static const struct efx_ethtool_stat efx_ethtool_stats[] = {
		EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_tcp_udp_chksum_err),
		EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_mcast_mismatch),
		EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_frm_trunc),
		EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_nodesc_trunc),
		};

		/* Number of ethtool statistics */
		@@ -978,7 +979,8 @@ static int efx_ethtool_set_class_rule(struct efx_nic *efx,
		rule->m_ext.data[1]))
		return -EINVAL;

		efx_filter_init_rx(&spec, EFX_FILTER_PRI_MANUAL, 0,
		efx_filter_init_rx(&spec, EFX_FILTER_PRI_MANUAL,
		efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0,
		(rule->ring_cookie == RX_CLS_FLOW_DISC) ?
		0xfff : rule->ring_cookie);

drivers/net/ethernet/sfc/falcon.c

+10 −7

Original line number	Diff line number	Diff line
		@@ -1546,10 +1546,6 @@ static int falcon_probe_nic(struct efx_nic *efx)

		static void falcon_init_rx_cfg(struct efx_nic *efx)
		{
		/* Prior to Siena the RX DMA engine will split each frame at
		* intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
		* be so large that that never happens. */
		const unsigned huge_buf_size = (3 * 4096) >> 5;
		/* RX control FIFO thresholds (32 entries) */
		const unsigned ctrl_xon_thr = 20;
		const unsigned ctrl_xoff_thr = 25;
		@@ -1557,10 +1553,15 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)

		efx_reado(efx, &reg, FR_AZ_RX_CFG);
		if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
		/* Data FIFO size is 5.5K */
		/* Data FIFO size is 5.5K. The RX DMA engine only
		* supports scattering for user-mode queues, but will
		* split DMA writes at intervals of RX_USR_BUF_SIZE
		* (32-byte units) even for kernel-mode queues. We
		* set it to be so large that that never happens.
		*/
		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
		huge_buf_size);
		(3 * 4096) >> 5);
		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
		@@ -1569,7 +1570,7 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
		/* Data FIFO size is 80K; register fields moved */
		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
		huge_buf_size);
		EFX_RX_USR_BUF_SIZE >> 5);
		/* Send XON and XOFF at ~3 * max MTU away from empty/full */
		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
		@@ -1815,6 +1816,7 @@ const struct efx_nic_type falcon_a1_nic_type = {
		.evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
		.max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
		.rx_buffer_padding = 0x24,
		.can_rx_scatter = false,
		.max_interrupt_mode = EFX_INT_MODE_MSI,
		.phys_addr_channels = 4,
		.timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
		@@ -1865,6 +1867,7 @@ const struct efx_nic_type falcon_b0_nic_type = {
		.max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
		.rx_buffer_hash_size = 0x10,
		.rx_buffer_padding = 0,
		.can_rx_scatter = true,
		.max_interrupt_mode = EFX_INT_MODE_MSIX,
		.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
		* interrupt handler only supports 32

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