Commit 300387c0 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Clear the vblank status bit before polling for the next vblank



The vblank status bit is a sticky bit that must be cleared with a write
of '1' prior to polling for the next vblank.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Tested-by: default avatarSitsofe Wheeler <sitsofe@yahoo.com>

jbarnes: I'd still rather see a lock, but I think you're right that
we don't generally wait in code that needs not to miss an interrupt.
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent 4f233eff
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+16 −0
Original line number Diff line number Diff line
@@ -990,6 +990,22 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);

	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

	/* Wait for vblank interrupt bit to set */
	if (wait_for((I915_READ(pipestat_reg) &
		      PIPE_VBLANK_INTERRUPT_STATUS),