drm/i915/fbc: Make fence_id optional for i965gm (30016696) · Commits · 戴 / test

i965gm no longer needs the fence for scanout so we should be do what we do for ctg+ and only configure a fence for FBC when we have one. In theory this should do nothing atm on account of intel_fbc_can_activate() requiring the fence, but since we do this for g4x+ let's do it for i965gm as well. We may want to relax the requirements at some point and allow FBC without a fence. Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191127201222.16669-9-ville.syrjala@linux.intel.com Reviewed-by:

Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

drivers/gpu/drm/i915/display/intel_fbc.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -138,8 +138,10 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
		u32 fbc_ctl2;

		/* Set it up... */
		fbc_ctl2 = FBC_CTL_FENCE_DBL \| FBC_CTL_IDLE_IMM \| FBC_CTL_CPU_FENCE;
		fbc_ctl2 = FBC_CTL_FENCE_DBL \| FBC_CTL_IDLE_IMM;
		fbc_ctl2 \|= FBC_CTL_PLANE(params->crtc.i9xx_plane);
		if (params->fence_id >= 0)
		fbc_ctl2 \|= FBC_CTL_CPU_FENCE;
		I915_WRITE(FBC_CONTROL2, fbc_ctl2);
		I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
		}
		@@ -151,6 +153,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
		if (IS_I945GM(dev_priv))
		fbc_ctl \|= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
		fbc_ctl \|= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
		if (params->fence_id >= 0)
		fbc_ctl \|= params->fence_id;
		I915_WRITE(FBC_CONTROL, fbc_ctl);
		}

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