Commit 2fcb12df authored by Inbar Karmy's avatar Inbar Karmy Committed by Saeed Mahameed
Browse files

net/mlx5e: Expose PFC stall prevention counters 



Add the needed capability bit and counters to device spec description.
Expose the following two counters in ethtool:

tx_pause_storm_warning_events: when the device is stalled for a period
longer than a pre-configured watermark, the counter increase, allowing
the debug utility an insight into current device status.

tx_pause_storm_error_events: when the device is stalled for a period
longer than a pre-configured timeout, the pause transmission is disabled,
and the counter increase.

Signed-off-by: default avatarInbar Karmy <inbark@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 336f2c03

drivers/net/ethernet/mellanox/mlx5/core/en_stats.c

+18 −1
Original line number Diff line number Diff line
@@ -754,7 +754,15 @@ static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 
	{ "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },

};



static const struct counter_desc pport_pfc_stall_stats_desc[] = {

	{ "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },

	{ "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },

};



#define NUM_PPORT_PER_PRIO_PFC_COUNTERS		ARRAY_SIZE(pport_per_prio_pfc_stats_desc)

#define NUM_PPORT_PFC_STALL_COUNTERS(priv)	(ARRAY_SIZE(pport_pfc_stall_stats_desc) * \

						 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \

						 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))



static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)

{
@@ -790,7 +798,8 @@ static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv) 
{

	return (mlx5e_query_global_pause_combined(priv) +

		hweight8(mlx5e_query_pfc_combined(priv))) *

		NUM_PPORT_PER_PRIO_PFC_COUNTERS;

		NUM_PPORT_PER_PRIO_PFC_COUNTERS +

		NUM_PPORT_PFC_STALL_COUNTERS(priv);

}



static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
@@ -818,6 +827,10 @@ static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, 
		}

	}



	for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)

		strcpy(data + (idx++) * ETH_GSTRING_LEN,

		       pport_pfc_stall_stats_desc[i].format);



	return idx;

}
@@ -845,6 +858,10 @@ static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv, 
		}

	}



	for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)

		data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],

						  pport_pfc_stall_stats_desc, i);



	return idx;

}

drivers/net/ethernet/mellanox/mlx5/core/fw.c

+3 −0
Original line number Diff line number Diff line
@@ -183,6 +183,9 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 
			return err;

	}



	if (MLX5_CAP_GEN(dev, debug))

		mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);



	if (MLX5_CAP_GEN(dev, pcam_reg))

		mlx5_get_pcam_reg(dev);

include/linux/mlx5/device.h

+4 −0
Original line number Diff line number Diff line
@@ -1013,6 +1013,7 @@ enum mlx5_cap_type { 
	MLX5_CAP_RESERVED,

	MLX5_CAP_VECTOR_CALC,

	MLX5_CAP_QOS,

	MLX5_CAP_DEBUG,

	/* NUM OF CAP Types */

	MLX5_CAP_NUM

};
@@ -1140,6 +1141,9 @@ enum mlx5_qcam_feature_groups { 
#define MLX5_CAP_QOS(mdev, cap)\

	MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)



#define MLX5_CAP_DEBUG(mdev, cap)\

	MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)



#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \

	MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)

include/linux/mlx5/mlx5_ifc.h

+25 −3
Original line number Diff line number Diff line
@@ -593,6 +593,16 @@ struct mlx5_ifc_qos_cap_bits { 
	u8         reserved_at_100[0x700];

};



struct mlx5_ifc_debug_cap_bits {

	u8         reserved_at_0[0x20];



	u8         reserved_at_20[0x2];

	u8         stall_detect[0x1];

	u8         reserved_at_23[0x1d];



	u8         reserved_at_40[0x7c0];

};



struct mlx5_ifc_per_protocol_networking_offload_caps_bits {

	u8         csum_cap[0x1];

	u8         vlan_cap[0x1];
@@ -855,7 +865,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { 
	u8         out_of_seq_cnt[0x1];

	u8         vport_counters[0x1];

	u8         retransmission_q_counters[0x1];

	u8         reserved_at_183[0x1];

	u8         debug[0x1];

	u8         modify_rq_counter_set_id[0x1];

	u8         rq_delay_drop[0x1];

	u8         max_qp_cnt[0xa];
@@ -1572,7 +1582,17 @@ struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 


	u8         rx_pause_transition_low[0x20];



	u8         reserved_at_3c0[0x400];

	u8         reserved_at_3c0[0x40];



	u8         device_stall_minor_watermark_cnt_high[0x20];



	u8         device_stall_minor_watermark_cnt_low[0x20];



	u8         device_stall_critical_watermark_cnt_high[0x20];



	u8         device_stall_critical_watermark_cnt_low[0x20];



	u8         reserved_at_480[0x340];

};



struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
@@ -7874,8 +7894,10 @@ struct mlx5_ifc_peir_reg_bits { 
};



struct mlx5_ifc_pcam_enhanced_features_bits {

	u8         reserved_at_0[0x7b];

	u8         reserved_at_0[0x76];



	u8         pfcc_mask[0x1];

	u8         reserved_at_77[0x4];

	u8         rx_buffer_fullness_counters[0x1];

	u8         ptys_connector_type[0x1];

	u8         reserved_at_7d[0x1];

CRA Git | Maintained and supported by SUSTech CRA and CCSE