Commit 2fbc5bdc authored Mar 16, 2018 by Thinh Nguyen Committed by Felipe Balbi Mar 22, 2018

usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields



Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register
fields for DWC_usb31 is as follows:
 +-------+--------------------------+----------------------------------+
 | BITS  | Name                     | Description                      |
 +=======+==========================+==================================+
 | 31:27 | reserved                 |                                  |
 | 26    | UsbRxPktCntSel           | Async ESS receive packet         |
 |       |                          | threshold enable                 |
 | 25:21 | UsbRxPktCnt              | Async ESS receive packet         |
 |       |                          | threshold count                  |
 | 20:16 | UsbMaxRxBurstSize        | Async ESS Max receive burst size |
 | 15    | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic       |
 |       |                          | receive packet threshold enable  |
 | 14:13 | UsbRxThrNumPkt_HS_Prd    | HS high bandwidth periodic       |
 |       |                          | receive packet threshold count   |
 | 12:11 | reserved                 |                                  |
 | 10    | UsbRxThrNumPktSel_Prd    | Periodic ESS receive packet      |
 |       |                          | threshold enable                 |
 | 9:5   | UsbRxThrNumPkt_Prd       | Periodic ESS receive packet      |
 |       |                          | threshold count                  |
 | 4:0   | UsbMaxRxBurstSize_Prd    | Max periodic ESS RX burst size   |
 +-------+--------------------------+----------------------------------+

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

parent d548a617

drivers/usb/dwc3/core.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -178,6 +178,16 @@
		#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
		#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)

		/* Global RX Threshold Configuration Register for DWC_usb31 only */
		#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
		#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
		#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
		#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
		#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
		#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
		#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
		#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)

		/* Global Configuration Register */
		#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
		#define DWC3_GCTL_U2RSTECN BIT(16)

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