Commit 2fbae64a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.11' of... 

Merge tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock updates from Maxime Ripard:

  - Support for one new SoC, the V3s
  - Conversion of two old SoCs to the new framework, the old sun5i family
    and the A80
  - A bunch of fixes

* tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
  ARM: dts: sun9i: Switch to new clock bindings
  clk: sunxi-ng: Add A80 Display Engine CCU
  clk: sunxi-ng: Add A80 USB CCU
  clk: sunxi-ng: Add A80 CCU
  clk: sunxi-ng: Support separately grouped PLL lock status register
  clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
  clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
  clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
  clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU
  clk: sunxi-ng: Call divider_round_rate if we only have a single parent
  ARM: gr8: Convert to CCU
  ARM: sun5i: Convert to CCU
  clk: sunxi-ng: Add sun5i CCU driver
  clk: sunxi-ng: Implement global pre-divider
  clk: sunxi-ng: Implement multiplier maximum
  clk: sunxi-ng: mult: Fix minimum in round rate
  clk: sunxi-ng: Implement factors offsets
  clk: sunxi-ng: multiplier: Add fractional support
  clk: sunxi-ng: add support for V3s CCU
  dt-bindings: add device binding for the CCU of Allwinner V3s
  ...
parents eaff16bc 64507fe3

Documentation/devicetree/bindings/clock/sun9i-de.txt

0 → 100644
+28 −0
Original line number Original line Diff line number Diff line 
Allwinner A80 Display Engine Clock Control Binding

--------------------------------------------------



Required properties :

- compatible: must contain one of the following compatibles:

		- "allwinner,sun9i-a80-de-clks"



- reg: Must contain the registers base address and length

- clocks: phandle to the clocks feeding the display engine subsystem.

	  Three are needed:

  - "mod": the display engine module clock

  - "dram": the DRAM bus clock for the system

  - "bus": the bus clock for the whole display engine subsystem

- clock-names: Must contain the clock names described just above

- resets: phandle to the reset control for the display engine subsystem.

- #clock-cells : must contain 1

- #reset-cells : must contain 1



Example:

de_clocks: clock@3000000 {

	compatible = "allwinner,sun9i-a80-de-clks";

	reg = <0x03000000 0x30>;

	clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;

	clock-names = "mod", "dram", "bus";

	resets = <&ccu RST_BUS_DE>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/clock/sun9i-usb.txt

0 → 100644
+24 −0
Original line number Original line Diff line number Diff line 
Allwinner A80 USB Clock Control Binding

---------------------------------------



Required properties :

- compatible: must contain one of the following compatibles:

		- "allwinner,sun9i-a80-usb-clocks"



- reg: Must contain the registers base address and length

- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:

  - "bus": the bus clock for the whole USB subsystem

  - "hosc": the high frequency oscillator (usually at 24MHz)

- clock-names: Must contain the clock names described just above

- #clock-cells : must contain 1

- #reset-cells : must contain 1



Example:

usb_clocks: clock@a08000 {

	compatible = "allwinner,sun9i-a80-usb-clks";

	reg = <0x00a08000 0x8>;

	clocks = <&ccu CLK_BUS_USB>, <&osc24M>;

	clock-names = "bus", "hosc";

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,8 @@ Required properties : 
		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a33-ccu"

		- "allwinner,sun8i-a33-ccu"

		- "allwinner,sun8i-h3-ccu"

		- "allwinner,sun8i-h3-ccu"

		- "allwinner,sun8i-v3s-ccu"

		- "allwinner,sun9i-a80-ccu"

		- "allwinner,sun50i-a64-ccu"

		- "allwinner,sun50i-a64-ccu"





- reg: Must contain the registers base address and length

- reg: Must contain the registers base address and length

arch/arm/boot/dts/sun5i-a10s.dtsi

+16 −69
Original line number Original line Diff line number Diff line
@@ -65,8 +65,9 @@ 
			compatible = "allwinner,simple-framebuffer",

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-hdmi";

			allwinner,pipeline = "de_be0-lcd0-hdmi";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,

			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,

				 <&ahb_gates 43>, <&ahb_gates 44>;

				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,

				 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -74,8 +75,8 @@ 
			compatible = "allwinner,simple-framebuffer",

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0";

			allwinner,pipeline = "de_be0-lcd0";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,

			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,

				 <&ahb_gates 44>;

				 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -83,77 +84,19 @@ 
			compatible = "allwinner,simple-framebuffer",

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-tve0";

			allwinner,pipeline = "de_be0-lcd0-tve0";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,

			clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,

				 <&ahb_gates 36>, <&ahb_gates 44>;

				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,

				 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;

			status = "disabled";

			status = "disabled";

		};

		};

	};

	};





	clocks {

		ahb_gates: clk@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a10s-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-indices = <0>, <1>,

					<2>, <5>, <6>,

					<7>, <8>, <9>,

					<10>, <13>,

					<14>, <17>, <18>,

					<20>, <21>, <22>,

					<26>, <28>, <32>,

					<34>, <36>, <40>,

					<43>, <44>,

					<46>, <51>,

					<52>;

			clock-output-names = "ahb_usbotg", "ahb_ehci",

					     "ahb_ohci", "ahb_ss", "ahb_dma",

					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",

					     "ahb_mmc2", "ahb_nand",

					     "ahb_sdram", "ahb_emac", "ahb_ts",

					     "ahb_spi0", "ahb_spi1", "ahb_spi2",

					     "ahb_gps", "ahb_stimer", "ahb_ve",

					     "ahb_tve", "ahb_lcd", "ahb_csi",

					     "ahb_hdmi", "ahb_de_be",

					     "ahb_de_fe", "ahb_iep",

					     "ahb_mali400";

		};



		apb0_gates: clk@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a10s-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-indices = <0>, <3>,

					<5>, <6>,

					<10>;

			clock-output-names = "apb0_codec", "apb0_iis",

					     "apb0_pio", "apb0_ir",

					     "apb0_keypad";

		};



		apb1_gates: clk@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a10s-apb1-gates-clk";

			reg = <0x01c2006c 0x4>;

			clocks = <&apb1>;

			clock-indices = <0>, <1>,

					<2>, <16>,

					<17>, <18>,

					<19>;

			clock-output-names = "apb1_i2c0", "apb1_i2c1",

					     "apb1_i2c2", "apb1_uart0",

					     "apb1_uart1", "apb1_uart2",

					     "apb1_uart3";

		};

	};



	soc@01c00000 {

	soc@01c00000 {

		emac: ethernet@01c0b000 {

		emac: ethernet@01c0b000 {

			compatible = "allwinner,sun4i-a10-emac";

			compatible = "allwinner,sun4i-a10-emac";

			reg = <0x01c0b000 0x1000>;

			reg = <0x01c0b000 0x1000>;

			interrupts = <55>;

			interrupts = <55>;

			clocks = <&ahb_gates 17>;

			clocks = <&ccu CLK_AHB_EMAC>;

			allwinner,sram = <&emac_sram 1>;

			allwinner,sram = <&emac_sram 1>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -169,7 +112,7 @@ 
		pwm: pwm@01c20e00 {

		pwm: pwm@01c20e00 {

			compatible = "allwinner,sun5i-a10s-pwm";

			compatible = "allwinner,sun5i-a10s-pwm";

			reg = <0x01c20e00 0xc>;

			reg = <0x01c20e00 0xc>;

			clocks = <&osc24M>;

			clocks = <&ccu CLK_HOSC>;

			#pwm-cells = <3>;

			#pwm-cells = <3>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -180,7 +123,7 @@ 
			interrupts = <1>;

			interrupts = <1>;

			reg-shift = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 16>;

			clocks = <&ccu CLK_APB1_UART0>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -190,12 +133,16 @@ 
			interrupts = <3>;

			interrupts = <3>;

			reg-shift = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 18>;

			clocks = <&ccu CLK_APB1_UART2>;

			status = "disabled";

			status = "disabled";

		};

		};

	};

	};

};

};





&ccu {

	compatible = "allwinner,sun5i-a10s-ccu";

};



&pio {

&pio {

	compatible = "allwinner,sun5i-a10s-pinctrl";

	compatible = "allwinner,sun5i-a10s-pinctrl";

arch/arm/boot/dts/sun5i-a13.dtsi

+18 −122
Original line number Original line Diff line number Diff line
@@ -61,8 +61,8 @@ 
			compatible = "allwinner,simple-framebuffer",

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0";

			allwinner,pipeline = "de_be0-lcd0";

			clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,

			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,

				 <&tcon_ch0_clk>, <&dram_gates 26>;

				 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;

			status = "disabled";

			status = "disabled";

		};

		};

	};

	};
@@ -99,114 +99,6 @@ 
		};

		};

	};

	};





	clocks {

		ahb_gates: clk@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-indices = <0>, <1>,

					<2>, <5>, <6>,

					<7>, <8>, <9>,

					<10>, <13>,

					<14>, <20>,

					<21>, <22>,

					<28>, <32>, <34>,

					<36>, <40>, <44>,

					<46>, <51>,

					<52>;

			clock-output-names = "ahb_usbotg", "ahb_ehci",

					     "ahb_ohci", "ahb_ss", "ahb_dma",

					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",

					     "ahb_mmc2", "ahb_nand",

					     "ahb_sdram", "ahb_spi0",

					     "ahb_spi1", "ahb_spi2",

					     "ahb_stimer", "ahb_ve", "ahb_tve",

					     "ahb_lcd", "ahb_csi", "ahb_de_be",

					     "ahb_de_fe", "ahb_iep",

					     "ahb_mali400";

		};



		apb0_gates: clk@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-indices = <0>, <5>,

					<6>;

			clock-output-names = "apb0_codec", "apb0_pio",

					     "apb0_ir";

		};



		apb1_gates: clk@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-apb1-gates-clk";

			reg = <0x01c2006c 0x4>;

			clocks = <&apb1>;

			clock-indices = <0>, <1>,

					<2>, <17>,

					<19>;

			clock-output-names = "apb1_i2c0", "apb1_i2c1",

					     "apb1_i2c2", "apb1_uart1",

					     "apb1_uart3";

		};



		dram_gates: clk@01c20100 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-dram-gates-clk",

				     "allwinner,sun4i-a10-gates-clk";

			reg = <0x01c20100 0x4>;

			clocks = <&pll5 0>;

			clock-indices = <0>,

					<1>,

					<25>,

					<26>,

					<29>,

					<31>;

			clock-output-names = "dram_ve",

					     "dram_csi",

					     "dram_de_fe",

					     "dram_de_be",

					     "dram_ace",

					     "dram_iep";

		};



		de_be_clk: clk@01c20104 {

			#clock-cells = <0>;

			#reset-cells = <0>;

			compatible = "allwinner,sun4i-a10-display-clk";

			reg = <0x01c20104 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll5 1>;

			clock-output-names = "de-be";

		};



		de_fe_clk: clk@01c2010c {

			#clock-cells = <0>;

			#reset-cells = <0>;

			compatible = "allwinner,sun4i-a10-display-clk";

			reg = <0x01c2010c 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll5 1>;

			clock-output-names = "de-fe";

		};



		tcon_ch0_clk: clk@01c20118 {

			#clock-cells = <0>;

			#reset-cells = <1>;

			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";

			reg = <0x01c20118 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;

			clock-output-names = "tcon-ch0-sclk";

		};



		tcon_ch1_clk: clk@01c2012c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";

			reg = <0x01c2012c 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;

			clock-output-names = "tcon-ch1-sclk";

		};

	};



	display-engine {

	display-engine {

		compatible = "allwinner,sun5i-a13-display-engine";

		compatible = "allwinner,sun5i-a13-display-engine";

		allwinner,pipelines = <&fe0>;

		allwinner,pipelines = <&fe0>;
@@ -217,11 +109,11 @@ 
			compatible = "allwinner,sun5i-a13-tcon";

			compatible = "allwinner,sun5i-a13-tcon";

			reg = <0x01c0c000 0x1000>;

			reg = <0x01c0c000 0x1000>;

			interrupts = <44>;

			interrupts = <44>;

			resets = <&tcon_ch0_clk 1>;

			resets = <&ccu RST_LCD>;

			reset-names = "lcd";

			reset-names = "lcd";

			clocks = <&ahb_gates 36>,

			clocks = <&ccu CLK_AHB_LCD>,

				 <&tcon_ch0_clk>,

				 <&ccu CLK_TCON_CH0>,

				 <&tcon_ch1_clk>;

				 <&ccu CLK_TCON_CH1>;

			clock-names = "ahb",

			clock-names = "ahb",

				      "tcon-ch0",

				      "tcon-ch0",

				      "tcon-ch1";

				      "tcon-ch1";
@@ -254,7 +146,7 @@ 
		pwm: pwm@01c20e00 {

		pwm: pwm@01c20e00 {

			compatible = "allwinner,sun5i-a13-pwm";

			compatible = "allwinner,sun5i-a13-pwm";

			reg = <0x01c20e00 0xc>;

			reg = <0x01c20e00 0xc>;

			clocks = <&osc24M>;

			clocks = <&ccu CLK_HOSC>;

			#pwm-cells = <3>;

			#pwm-cells = <3>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -263,11 +155,11 @@ 
			compatible = "allwinner,sun5i-a13-display-frontend";

			compatible = "allwinner,sun5i-a13-display-frontend";

			reg = <0x01e00000 0x20000>;

			reg = <0x01e00000 0x20000>;

			interrupts = <47>;

			interrupts = <47>;

			clocks = <&ahb_gates 46>, <&de_fe_clk>,

			clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,

				 <&dram_gates 25>;

				 <&ccu CLK_DRAM_DE_FE>;

			clock-names = "ahb", "mod",

			clock-names = "ahb", "mod",

				      "ram";

				      "ram";

			resets = <&de_fe_clk>;

			resets = <&ccu RST_DE_FE>;

			status = "disabled";

			status = "disabled";





			ports {

			ports {
@@ -290,14 +182,14 @@ 
		be0: display-backend@01e60000 {

		be0: display-backend@01e60000 {

			compatible = "allwinner,sun5i-a13-display-backend";

			compatible = "allwinner,sun5i-a13-display-backend";

			reg = <0x01e60000 0x10000>;

			reg = <0x01e60000 0x10000>;

			clocks = <&ahb_gates 44>, <&de_be_clk>,

			clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,

				 <&dram_gates 26>;

				 <&ccu CLK_DRAM_DE_BE>;

			clock-names = "ahb", "mod",

			clock-names = "ahb", "mod",

				      "ram";

				      "ram";

			resets = <&de_be_clk>;

			resets = <&ccu RST_DE_BE>;

			status = "disabled";

			status = "disabled";





			assigned-clocks = <&de_be_clk>;

			assigned-clocks = <&ccu CLK_DE_BE>;

			assigned-clock-rates = <300000000>;

			assigned-clock-rates = <300000000>;





			ports {

			ports {
@@ -330,6 +222,10 @@ 
	};

	};

};

};





&ccu {

	compatible = "allwinner,sun5i-a13-ccu";

};



&cpu0 {

&cpu0 {

	clock-latency = <244144>; /* 8 32k periods */

	clock-latency = <244144>; /* 8 32k periods */

	operating-points = <

	operating-points = <

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