Commit 2f9e8973 authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by Ingo Molnar
Browse files

x86/mm/mtrr, pat: Document Write Combining MTRR type effects on PAT / non-PAT pages 



As part of the effort to phase out MTRR use document
write-combining MTRR effects on pages with different non-PAT
page attributes flags and different PAT entry values. Extend
arch_phys_wc_add() documentation to clarify power of two sizes /
boundary requirements as we phase out mtrr_add() use.

Lastly hint towards ioremap_uc() for corner cases on device
drivers working with devices with mixed regions where MTRR size
requirements would otherwise not enable write-combining
effective memory types.

Signed-off-by: default avatarLuis R. Rodriguez <mcgrof@suse.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Antonino Daplas <adaplas@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Davidlohr Bueso <dbueso@suse.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suresh Siddha <sbsiddha@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Ville Syrjälä <syrjala@sci.fi>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: linux-fbdev@vger.kernel.org
Link: http://lkml.kernel.org/r/1430343851-967-3-git-send-email-mcgrof@do-not-panic.com
Link: http://lkml.kernel.org/r/1432628901-18044-10-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 9e76561f

Documentation/x86/mtrr.txt

+15 −3
Original line number Diff line number Diff line 
MTRR (Memory Type Range Register) control

3 Jun 1999

Richard Gooch

<rgooch@atnf.csiro.au>



Richard Gooch <rgooch@atnf.csiro.au> - 3 Jun 1999

Luis R. Rodriguez <mcgrof@do-not-panic.com> - April 9, 2015



===============================================================================

Phasing out MTRR use



MTRR use is replaced on modern x86 hardware with PAT. Over time the only type

of effective MTRR that is expected to be supported will be for write-combining.

As MTRR use is phased out device drivers should use arch_phys_wc_add() to make

MTRR effective on non-PAT systems while a no-op on PAT enabled systems.



For details refer to Documentation/x86/pat.txt.



===============================================================================



  On Intel P6 family processors (Pentium Pro, Pentium II and later)

  the Memory Type Range Registers (MTRRs) may be used to control

Documentation/x86/pat.txt

+34 −1
Original line number Diff line number Diff line
@@ -34,6 +34,8 @@ ioremap | -- | UC- | UC- | 
                       |          |            |                  |

ioremap_cache          |    --    |    WB      |       WB         |

                       |          |            |                  |

ioremap_uc             |    --    |    UC      |       UC         |

                       |          |            |                  |

ioremap_nocache        |    --    |    UC-     |       UC-        |

                       |          |            |                  |

ioremap_wc             |    --    |    --      |       WC         |
@@ -102,7 +104,38 @@ wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc() 
as step 0 above and also track the usage of those pages and use set_memory_wb()

before the page is freed to free pool.





MTRR effects on PAT / non-PAT systems

-------------------------------------



The following table provides the effects of using write-combining MTRRs when

using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally

mtrr_add() usage will be phased out in favor of arch_phys_wc_add() which will

be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()

is made, should already have been ioremapped with WC attributes or PAT entries,

this can be done by using ioremap_wc() / set_memory_wc().  Devices which

combine areas of IO memory desired to remain uncacheable with areas where

write-combining is desirable should consider use of ioremap_uc() followed by

set_memory_wc() to white-list effective write-combined areas.  Such use is

nevertheless discouraged as the effective memory type is considered

implementation defined, yet this strategy can be used as last resort on devices

with size-constrained regions where otherwise MTRR write-combining would

otherwise not be effective.



----------------------------------------------------------------------

MTRR Non-PAT   PAT    Linux ioremap value        Effective memory type

----------------------------------------------------------------------

                                                  Non-PAT |  PAT

     PAT

     |PCD

     ||PWT

     |||

WC   000      WB      _PAGE_CACHE_MODE_WB            WC   |   WC

WC   001      WC      _PAGE_CACHE_MODE_WC            WC*  |   WC

WC   010      UC-     _PAGE_CACHE_MODE_UC_MINUS      WC*  |   UC

WC   011      UC      _PAGE_CACHE_MODE_UC            UC   |   UC

----------------------------------------------------------------------



(*) denotes implementation defined and is discouraged



Notes:

arch/x86/kernel/cpu/mtrr/main.c

+3 −0
Original line number Diff line number Diff line
@@ -538,6 +538,9 @@ EXPORT_SYMBOL(mtrr_del); 
 * attempts to add a WC MTRR covering size bytes starting at base and

 * logs an error if this fails.

 *

 * The called should provide a power of two size on an equivalent

 * power of two boundary.

 *

 * Drivers must store the return value to pass to mtrr_del_wc_if_needed,

 * but drivers should not try to interpret that return value.

 */

CRA Git | Maintained and supported by SUSTech CRA and CCSE