drm/hisilicon/hibmc: add gamma_set function (2f89f37f) · Commits · 戴 / test

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

+37 −0

Original line number	Diff line number	Diff line
		@@ -454,6 +454,42 @@ static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc)
		priv->mmio + HIBMC_RAW_INTERRUPT_EN);
		}

		static void hibmc_crtc_load_lut(struct drm_crtc *crtc)
		{
		struct hibmc_drm_private *priv = crtc->dev->dev_private;
		void __iomem *mmio = priv->mmio;
		u16 r, g, *b;
		unsigned int reg;
		int i;

		r = crtc->gamma_store;
		g = r + crtc->gamma_size;
		b = g + crtc->gamma_size;

		for (i = 0; i < crtc->gamma_size; i++) {
		unsigned int offset = i << 2;
		u8 red = *r++ >> 8;
		u8 green = *g++ >> 8;
		u8 blue = *b++ >> 8;
		u32 rgb = (red << 16) \| (green << 8) \| blue;

		writel(rgb, mmio + HIBMC_CRT_PALETTE + offset);
		}

		reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
		reg \|= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1);
		writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
		}

		static int hibmc_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		u16 *blue, uint32_t size,
		struct drm_modeset_acquire_ctx *ctx)
		{
		hibmc_crtc_load_lut(crtc);

		return 0;
		}

		static const struct drm_crtc_funcs hibmc_crtc_funcs = {
		.page_flip = drm_atomic_helper_page_flip,
		.set_config = drm_atomic_helper_set_config,
		@@ -463,6 +499,7 @@ static const struct drm_crtc_funcs hibmc_crtc_funcs = {
		.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
		.enable_vblank = hibmc_crtc_enable_vblank,
		.disable_vblank = hibmc_crtc_disable_vblank,
		.gamma_set = hibmc_crtc_gamma_set,
		};

		static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = {

+5 −0

Original line number	Diff line number	Diff line
		@@ -91,6 +91,9 @@
		#define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8)
		#define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100

		#define HIBMC_CTL_DISP_CTL_GAMMA(x) ((x) << 3)
		#define HIBMC_CTL_DISP_CTL_GAMMA_MASK 0x08

		#define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2)
		#define HIBMC_CRT_DISP_CTL_PLANE_MASK 4

		@@ -193,5 +196,7 @@
		#define CRT_PLL2_HS_148MHZ 0xB0CCCCCD
		#define CRT_PLL2_HS_193MHZ 0xC0872B02

		#define HIBMC_CRT_PALETTE 0x80C00

		#define HIBMC_FIELD(field, value) (field(value) & field##_MASK)
		#endif