Commit 2f81137f authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

arm64: dts: uniphier: switch over to PSCI enable method 



At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent a909d3e6

arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

+8 −5
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */

/memreserve/ 0x80000000 0x00080000;



/ {

	compatible = "socionext,uniphier-ld11";
@@ -70,19 +70,22 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x000>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			enable-method = "psci";

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x001>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			enable-method = "psci";

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+10 −9
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */

/memreserve/ 0x80000000 0x00080000;



/ {

	compatible = "socionext,uniphier-ld20";
@@ -79,35 +79,36 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0 0x000>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			enable-method = "psci";

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0 0x001>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			enable-method = "psci";

		};



		cpu2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			enable-method = "psci";

		};



		cpu3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			enable-method = "psci";

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";

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