Commit 2f752e91 authored by Nikola Cornij's avatar Nikola Cornij Committed by Alex Deucher
Browse files

drm/amd/display: Remove connect DIG FE to its BE during timing programming 



[why]
Causes regression with MST DSC displays not lighting up after DPMS

[how]
Revert commit 8cc426d7 ("drm/amd/display: Program DSC during timing programming")

Signed-off-by: default avatarNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0aa63a33

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+3 −8
Original line number Diff line number Diff line
@@ -3069,14 +3069,9 @@ void core_link_enable_stream( 


		if (pipe_ctx->stream->timing.flags.DSC) {

			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

					dc_is_virtual_signal(pipe_ctx->stream->signal)) {

				/* Here we only need to enable DSC on RX. DSC HW programming

				 * was done earlier, as part of timing programming.

				 */

				dp_set_dsc_on_rx(pipe_ctx, true);

			}

					dc_is_virtual_signal(pipe_ctx->stream->signal))

				dp_set_dsc_enable(pipe_ctx, true);

		}



		dc->hwss.enable_stream(pipe_ctx);



		/* Set DPS PPS SDP (AKA "info frames") */
@@ -3103,7 +3098,7 @@ void core_link_enable_stream( 
	} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

				dc_is_virtual_signal(pipe_ctx->stream->signal))

			dp_set_dsc_on_rx(pipe_ctx, true);

			dp_set_dsc_enable(pipe_ctx, true);



	}

}

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+1 −1
Original line number Diff line number Diff line
@@ -394,7 +394,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, 
	DC_LOG_DSC("\tslice_width %d", config->slice_width);

}



bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

{

	struct dc *dc = pipe_ctx->stream->ctx->dc;

	struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+0 −7
Original line number Diff line number Diff line
@@ -623,13 +623,6 @@ enum dc_status dcn20_enable_stream_timing( 


	/* TODO check if timing_changed, disable stream if timing changed */



	/* Have to setup DSC here to make sure the bandwidth sent to DIG BE won't be bigger than

	 * what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag will be automatically

	 * set at a later time when the video is enabled (DP_VID_STREAM_EN = 1).

	 */

	if (pipe_ctx->stream->timing.flags.DSC)

		dp_set_dsc_on_stream(pipe_ctx, true);



	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

		opp_cnt++;

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

+0 −1
Original line number Diff line number Diff line
@@ -85,7 +85,6 @@ void dp_set_fec_enable(struct dc_link *link, bool enable); 
bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);

bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);

void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);

bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);



#endif /* __DC_LINK_DP_H__ */

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