Commit 2f7460a7 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915: Align vswing sequences with old ddi buffer registers. 



Vswing sequences on BXT and CNL are equivalent
to the ddi buffer registers setting on other platforms.

For some reason it got aligned with skl_ddi_set_iboost what
is semantically incorrect. This forced us to keep skipping
ddi buffer translation tables on the platforms that has
the vswing sequences.

v2: Don't mess with DP signal levels on this patch.

Cc: Vandana Kannan <vandana.kannan@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-3-rodrigo.vivi@intel.com
parent d509af6c

drivers/gpu/drm/i915/intel_ddi.c

+10 −12
Original line number Original line Diff line number Diff line
@@ -688,9 +688,6 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) 
	enum port port = intel_ddi_get_encoder_port(encoder);

	enum port port = intel_ddi_get_encoder_port(encoder);

	const struct ddi_buf_trans *ddi_translations;

	const struct ddi_buf_trans *ddi_translations;





	if (IS_GEN9_LP(dev_priv))

		return;



	switch (encoder->type) {

	switch (encoder->type) {

	case INTEL_OUTPUT_EDP:

	case INTEL_OUTPUT_EDP:

		ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,

		ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
@@ -741,9 +738,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) 
	enum port port = intel_ddi_get_encoder_port(encoder);

	enum port port = intel_ddi_get_encoder_port(encoder);

	const struct ddi_buf_trans *ddi_translations_hdmi;

	const struct ddi_buf_trans *ddi_translations_hdmi;





	if (IS_GEN9_LP(dev_priv))

		return;



	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);

	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);





	if (IS_GEN9_BC(dev_priv)) {

	if (IS_GEN9_BC(dev_priv)) {
@@ -2154,7 +2148,9 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 




	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);





	if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))

		intel_prepare_dp_ddi_buffers(encoder);

		intel_prepare_dp_ddi_buffers(encoder);



	intel_ddi_init_dp_buf_reg(encoder);

	intel_ddi_init_dp_buf_reg(encoder);

	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);

	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);

	intel_dp_start_link_train(intel_dp);

	intel_dp_start_link_train(intel_dp);
@@ -2180,14 +2176,16 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 




	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);





	intel_prepare_hdmi_ddi_buffers(encoder);

	if (IS_CANNONLAKE(dev_priv))

	if (IS_GEN9_BC(dev_priv))

		cnl_ddi_vswing_sequence(encoder, level);

		skl_ddi_set_iboost(encoder, level);

	else if (IS_GEN9_LP(dev_priv))

	else if (IS_GEN9_LP(dev_priv))

		bxt_ddi_vswing_sequence(dev_priv, level, port,

		bxt_ddi_vswing_sequence(dev_priv, level, port,

					INTEL_OUTPUT_HDMI);

					INTEL_OUTPUT_HDMI);

	else if (IS_CANNONLAKE(dev_priv))

	else

		cnl_ddi_vswing_sequence(encoder, level);

		intel_prepare_hdmi_ddi_buffers(encoder);



	if (IS_GEN9_BC(dev_priv))

		skl_ddi_set_iboost(encoder, level);





	intel_dig_port->set_infoframes(&encoder->base,

	intel_dig_port->set_infoframes(&encoder->base,

				       has_infoframe,

				       has_infoframe,

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