Commit 2f6df34c authored by Mark Rankilor's avatar Mark Rankilor Committed by Greg Kroah-Hartman
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Staging: comedi: Checkpatch cleanups in adl_pci9111.c 



This patch cleans up some various warnings generated from checkpatch.pl

Signed-off-by: default avatarMark Rankilor <reodge@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent f25bd6bf

drivers/staging/comedi/drivers/adl_pci9111.c

+59 −46
Original line number Diff line number Diff line
@@ -68,8 +68,9 @@ CHANGELOG: 
TODO:



  - Really test implemented functionality.

  - Add support for the PCI-9111DG with a probe routine to identify the card type

    (perhaps with the help of the channel number readback of the A/D Data register).

  - Add support for the PCI-9111DG with a probe routine to identify the card

    type (perhaps with the help of the channel number readback of the A/D Data

    register).

  - Add external multiplexer support.



*/
@@ -134,11 +135,13 @@ TODO: 


/* IO address map */



#define PCI9111_REGISTER_AD_FIFO_VALUE 			0x00	/*  AD Data stored in FIFO */

#define PCI9111_REGISTER_AD_FIFO_VALUE			0x00 /* AD Data stored

								in FIFO */

#define PCI9111_REGISTER_DA_OUTPUT			0x00

#define PCI9111_REGISTER_DIGITAL_IO			0x02

#define PCI9111_REGISTER_EXTENDED_IO_PORTS		0x04

#define PCI9111_REGISTER_AD_CHANNEL_CONTROL 		0x06	/*  Channel selection */

#define PCI9111_REGISTER_AD_CHANNEL_CONTROL		0x06 /* Channel

								selection */

#define PCI9111_REGISTER_AD_CHANNEL_READBACK		0x06

#define PCI9111_REGISTER_INPUT_SIGNAL_RANGE		0x08

#define PCI9111_REGISTER_RANGE_STATUS_READBACK		0x08
@@ -177,7 +180,7 @@ TODO: 
#define PCI9111_FIFO_FULL_MASK				0x40

#define PCI9111_AD_BUSY_MASK				0x80



#define PCI9111_IO_BASE dev->iobase

#define PCI9111_IO_BASE (dev->iobase)



/*

 * Define inlined function
@@ -190,7 +193,8 @@ TODO: 
  outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_TRIGGER_MODE_CONTROL)



#define pci9111_interrupt_and_fifo_get()				   \

  ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK) >> 4) &0x03)

  ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK) >> 4) \

   &0x03)



#define pci9111_interrupt_and_fifo_set(flags) \

  outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL)
@@ -201,10 +205,14 @@ TODO: 
#define pci9111_software_trigger() \

  outb(0, PCI9111_IO_BASE+PCI9111_REGISTER_SOFTWARE_TRIGGER)



#define pci9111_fifo_reset() \

  outb(PCI9111_FFEN_SET_FIFO_ENABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \

  outb(PCI9111_FFEN_SET_FIFO_DISABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \

  outb(PCI9111_FFEN_SET_FIFO_ENABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL)

#define pci9111_fifo_reset() do {					\

  outb(PCI9111_FFEN_SET_FIFO_ENABLE,					\

       PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL);		\

  outb(PCI9111_FFEN_SET_FIFO_DISABLE,					\

       PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL);		\

  outb(PCI9111_FFEN_SET_FIFO_ENABLE,					\

       PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL);		\

  } while (0)



#define pci9111_is_fifo_full() \

  ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
@@ -219,20 +227,25 @@ TODO: 
    PCI9111_FIFO_EMPTY_MASK) == 0)



#define pci9111_ai_channel_set(channel)					\

  outb((channel)&PCI9111_CHANNEL_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_CONTROL)

  outb((channel)&PCI9111_CHANNEL_MASK,					\

       PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_CONTROL)



#define pci9111_ai_channel_get()					\

  inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_READBACK)&PCI9111_CHANNEL_MASK

  (inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_READBACK)		\

   &PCI9111_CHANNEL_MASK)



#define pci9111_ai_range_set(range)					\

  outb((range)&PCI9111_RANGE_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_INPUT_SIGNAL_RANGE)

  outb((range)&PCI9111_RANGE_MASK,					\

       PCI9111_IO_BASE+PCI9111_REGISTER_INPUT_SIGNAL_RANGE)



#define pci9111_ai_range_get()						\

  inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)&PCI9111_RANGE_MASK

  (inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)		\

   &PCI9111_RANGE_MASK)



#define pci9111_ai_get_data()						\

  ((inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE)>>4)&PCI9111_AI_RESOLUTION_MASK) \

  ^ PCI9111_AI_RESOLUTION_2_CMP_BIT

  (((inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE)>>4)		\

    &PCI9111_AI_RESOLUTION_MASK)					\

   ^ PCI9111_AI_RESOLUTION_2_CMP_BIT)



#define pci9111_hr_ai_get_data() \

  (inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE) & PCI9111_HR_AI_RESOLUTION_MASK) \

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