powerpc/qspinlock: Optimised atomic_try_cmpxchg_lock() that adds the lock hint

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

#define atomic_xchg_relaxed(v, new) xchg_relaxed(&((v)->counter), (new))

/*

 * Don't want to override the generic atomic_try_cmpxchg_acquire, because

 * we add a lock hint to the lwarx, which may not be wanted for the

 * _acquire case (and is not used by the other _acquire variants so it

 * would be a surprise).

 */

static __always_inline bool

atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new)

{

	int r, o = *old;

	__asm__ __volatile__ (

"1:\t"	PPC_LWARX(%0,0,%2,1) "	# atomic_try_cmpxchg_acquire	\n"

"	cmpw	0,%0,%3							\n"

"	bne-	2f							\n"

"	stwcx.	%4,0,%2							\n"

"	bne-	1b							\n"

"\t"	PPC_ACQUIRE_BARRIER "						\n"

"2:									\n"

	: "=&r" (r), "+m" (v->counter)

	: "r" (&v->counter), "r" (o), "r" (new)

	: "cr0", "memory");

	if (unlikely(r != o))

		*old = r;

	return likely(r == o);

}

/**

 * atomic_fetch_add_unless - add unless the number is a given value

 * @v: pointer of type atomic_t

{

	u32 val = 0;

	if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL)))

	if (likely(atomic_try_cmpxchg_lock(&lock->val, &val, _Q_LOCKED_VAL)))

		return;

	queued_spin_lock_slowpath(lock, val);