Commit 2f0bf925 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-20121218' of git://github.com/czankel/xtensa-linux 

Pull Xtensa patchset from Chris Zankel:
 "This contains support of device trees, many fixes, and code clean-ups"

* tag 'xtensa-20121218' of git://github.com/czankel/xtensa-linux: (33 commits)
  xtensa: don't try to build DTB when OF is disabled
  xtensa: set the correct ethernet address for xtfpga
  xtensa: clean up files to make them code-style compliant
  xtensa: provide endianness macro for sparse
  xtensa: fix RASID SR initialization
  xtensa: initialize CPENABLE SR when core has one
  xtensa: reset all timers on initialization
  Use for_each_compatible_node() macro.
  xtensa: add XTFPGA DTS
  xtensa: add support for the XTFPGA boards
  xtensa: add device trees support
  xtensa: add IRQ domains support
  xtensa: add U-Boot image support (uImage).
  xtensa: clean up boot make rules
  xtensa: fix mb and wmb definitions
  xtensa: add s32c1i-based spinlock implementations
  xtensa: add s32c1i-based bitops implementations
  xtensa: add s32c1i-based atomic ops implementations
  xtensa: add s32c1i sanity check
  xtensa: add trap_set_handler function
  ...
parents 1bd12c91 055d4db1

Documentation/xtensa/atomctl.txt

0 → 100644
+44 −0
Original line number Diff line number Diff line 
We Have Atomic Operation Control (ATOMCTL) Register.

This register determines the effect of using a S32C1I instruction

with various combinations of:



     1. With and without an Coherent Cache Controller which

        can do Atomic Transactions to the memory internally.



     2. With and without An Intelligent Memory Controller which

        can do Atomic Transactions itself.



The Core comes up with a default value of for the three types of cache ops:



      0x28: (WB: Internal, WT: Internal, BY:Exception)



On the FPGA Cards we typically simulate an Intelligent Memory controller

which can implement  RCW transactions. For FPGA cards with an External

Memory controller we let it to the atomic operations internally while

doing a Cached (WB) transaction and use the Memory RCW for un-cached

operations.



For systems without an coherent cache controller, non-MX, we always

use the memory controllers RCW, thought non-MX controlers likely

support the Internal Operation.



CUSTOMER-WARNING:

   Virtually all customers buy their memory controllers from vendors that

   don't support atomic RCW memory transactions and will likely want to

   configure this register to not use RCW.



Developers might find using RCW in Bypass mode convenient when testing

with the cache being bypassed; for example studying cache alias problems.



See Section 4.3.12.4 of ISA; Bits:



                             WB     WT      BY

                           5   4 | 3   2 | 1   0

  2 Bit

  Field

  Values     WB - Write Back         WT - Write Thru         BY - Bypass

---------    ---------------         -----------------     ----------------

    0        Exception               Exception               Exception

    1        RCW Transaction         RCW Transaction         RCW Transaction

    2        Internal Operation      Exception               Reserved

    3        Reserved                Reserved                Reserved

arch/xtensa/Kconfig

+21 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ config XTENSA 
	select GENERIC_KERNEL_EXECVE

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select CLONE_BACKWARDS

	select IRQ_DOMAIN

	help

	  Xtensa processors are 32-bit RISC machines designed by Tensilica

	  primarily for embedded systems.  These processors are both
@@ -150,6 +151,15 @@ config XTENSA_PLATFORM_S6105 
	select SERIAL_CONSOLE

	select NO_IOPORT



config XTENSA_PLATFORM_XTFPGA

	bool "XTFPGA"

	select SERIAL_CONSOLE

	select ETHOC

	select XTENSA_CALIBRATE_CCOUNT

	help

	  XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).

	  This hardware is capable of running a full Linux distribution.



endchoice
@@ -177,6 +187,17 @@ config CMDLINE 
	  time by entering them here. As a minimum, you should specify the

	  memory size and the root device (e.g., mem=64M root=/dev/nfs).



config USE_OF

	bool "Flattened Device Tree support"

	select OF

	select OF_EARLY_FLATTREE

	help

	  Include support for flattened device tree machine descriptions.



config BUILTIN_DTB

	string "DTB to build into the kernel image"

	depends on OF



source "mm/Kconfig"



source "drivers/pcmcia/Kconfig"

arch/xtensa/Kconfig.debug

+21 −1
Original line number Diff line number Diff line
@@ -2,6 +2,26 @@ menu "Kernel hacking" 


source "lib/Kconfig.debug"



endmenu

config LD_NO_RELAX

	bool "Disable linker relaxation"

	default n

	help

	  Enable this function to disable link-time optimizations.

	  The default linker behavior is to combine identical literal

	  values to reduce code size and remove unnecessary overhead from

	  assembler-generated 'longcall' sequences.

	  Enabling this option improves the link time but increases the

	  code size, and possibly execution time.



config S32C1I_SELFTEST

	bool "Perform S32C1I instruction self-test at boot"

	default y

	help

	  Enable this option to test S32C1I instruction behavior at boot.

	  Correct operation of this instruction requires some cooperation from hardware

	  external to the processor (such as bus bridge, bus fabric, or memory controller).

	  It is easy to make wrong hardware configuration, this test should catch it early.



	  Say 'N' on stable hardware.



endmenu

arch/xtensa/Makefile

+19 −1
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ endif 
platform-$(CONFIG_XTENSA_PLATFORM_XT2000)	:= xt2000

platform-$(CONFIG_XTENSA_PLATFORM_ISS)		:= iss

platform-$(CONFIG_XTENSA_PLATFORM_S6105)	:= s6105

platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA)	:= xtfpga



PLATFORM = $(platform-y)

export PLATFORM
@@ -49,6 +50,17 @@ KBUILD_CFLAGS += -pipe -mlongcalls 


KBUILD_CFLAGS += $(call cc-option,-mforce-no-pic,)



ifneq ($(CONFIG_LD_NO_RELAX),)

LDFLAGS := --no-relax

endif



ifeq ($(shell echo -e __XTENSA_EB__ | $(CC) -E - | grep -v "\#"),1)

CHECKFLAGS += -D__XTENSA_EB__

endif

ifeq ($(shell echo -e __XTENSA_EL__ | $(CC) -E - | grep -v "\#"),1)

CHECKFLAGS += -D__XTENSA_EL__

endif



vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))

plfdirs := $(patsubst %,arch/xtensa/platforms/%/,$(platform-y))
@@ -75,6 +87,10 @@ core-y += $(buildvar) $(buildplf) 


libs-y		+= arch/xtensa/lib/ $(LIBGCC)



ifneq ($(CONFIG_BUILTIN_DTB),"")

core-$(CONFIG_OF) += arch/xtensa/boot/

endif



boot		:= arch/xtensa/boot



all: zImage
@@ -84,7 +100,9 @@ bzImage : zImage 
zImage: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) $@



%.dtb:

	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@



define archhelp

  @echo '* zImage      - Compressed kernel image (arch/xtensa/boot/images/zImage.*)'

endef

arch/xtensa/boot/Makefile

+24 −1
Original line number Diff line number Diff line
@@ -22,12 +22,35 @@ subdir-y := lib 
# Subdirs for the boot loader(s)



bootdir-$(CONFIG_XTENSA_PLATFORM_ISS)	 += boot-elf

bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf

bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf boot-uboot

bootdir-$(CONFIG_XTENSA_PLATFORM_XTFPGA) += boot-redboot boot-elf boot-uboot





BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o

ifneq ($(CONFIG_BUILTIN_DTB),"")

obj-$(CONFIG_OF) += $(BUILTIN_DTB)

endif



# Rule to build device tree blobs

$(obj)/%.dtb: $(src)/dts/%.dts FORCE

	$(call if_changed_dep,dtc)



clean-files := *.dtb.S



zImage Image: $(bootdir-y)



$(bootdir-y): $(addprefix $(obj)/,$(subdir-y)) \

	      $(addprefix $(obj)/,$(host-progs))

	$(Q)$(MAKE) $(build)=$(obj)/$@ $(MAKECMDGOALS)



OBJCOPYFLAGS = --strip-all -R .comment -R .note.gnu.build-id -O binary



vmlinux.bin: vmlinux FORCE

	$(call if_changed,objcopy)



vmlinux.bin.gz: vmlinux.bin FORCE

	$(call if_changed,gzip)



boot-elf: vmlinux.bin

boot-redboot: vmlinux.bin.gz

boot-uboot: vmlinux.bin.gz

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