Commit 2eee0229 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: support access regs outside of mmio bar 



add indirect access support to registers outside of
mmio bar.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f384ff95

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+9 −9
Original line number Diff line number Diff line
@@ -1003,9 +1003,9 @@ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 


void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,

			       uint32_t *buf, size_t size, bool write);

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,

			    uint32_t acc_flags);

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

			uint32_t acc_flags);

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags);
@@ -1025,8 +1025,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
 */

#define AMDGPU_REGS_NO_KIQ    (1<<1)



#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)

#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)



#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))

#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
@@ -1034,9 +1034,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))

#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))



#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)

#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
@@ -1073,7 +1073,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
		tmp_ |= ((val) & ~(mask));			\

		WREG32_PLL(reg, tmp_);				\

	} while (0)

#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))

#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))

#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))

#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+17 −28
Original line number Diff line number Diff line
@@ -298,10 +298,10 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 
}



/*

 * MMIO register access helper functions.

 * device register access helper functions.

 */

/**

 * amdgpu_mm_rreg - read a memory mapped IO register

 * amdgpu_device_rreg - read a register

 *

 * @adev: amdgpu_device pointer

 * @reg: dword aligned register offset
@@ -309,7 +309,7 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 
 *

 * Returns the 32 bit value from the offset specified.

 */

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,

			    uint32_t acc_flags)

{

	uint32_t ret;
@@ -319,15 +319,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 


	if ((reg * 4) < adev->rmmio_size)

		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));

	else {

		unsigned long flags;



		spin_lock_irqsave(&adev->mmio_idx_lock, flags);

		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));

		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));

		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);

	}

	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);

	else

		ret = adev->pcie_rreg(adev, (reg * 4));

	trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);

	return ret;

}
@@ -373,24 +367,19 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) 
		BUG();

}



void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t acc_flags)

void static inline amdgpu_device_wreg_no_kiq(struct amdgpu_device *adev, uint32_t reg,

					     uint32_t v, uint32_t acc_flags)

{

	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);

	trace_amdgpu_device_wreg(adev->pdev->device, reg, v);



	if ((reg * 4) < adev->rmmio_size)

		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));

	else {

		unsigned long flags;



		spin_lock_irqsave(&adev->mmio_idx_lock, flags);

		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));

		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));

		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);

	}

	else

		adev->pcie_wreg(adev, (reg * 4), v);

}



/**

 * amdgpu_mm_wreg - write to a memory mapped IO register

 * amdgpu_device_wreg - write to a register

 *

 * @adev: amdgpu_device pointer

 * @reg: dword aligned register offset
@@ -399,13 +388,13 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, 
 *

 * Writes the value specified to the offset specified.

 */

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

			uint32_t acc_flags)

{

	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))

		return amdgpu_kiq_wreg(adev, reg, v);



	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);

	amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);

}



/*
@@ -424,7 +413,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t 
			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);

	}



	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);

	amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

+2 −2
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
#define AMDGPU_JOB_GET_TIMELINE_NAME(job) \

	 job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)



TRACE_EVENT(amdgpu_mm_rreg,

TRACE_EVENT(amdgpu_device_rreg,

	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),

	    TP_ARGS(did, reg, value),

	    TP_STRUCT__entry(
@@ -54,7 +54,7 @@ TRACE_EVENT(amdgpu_mm_rreg, 
		      (unsigned long)__entry->value)

);



TRACE_EVENT(amdgpu_mm_wreg,

TRACE_EVENT(amdgpu_device_wreg,

	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),

	    TP_ARGS(did, reg, value),

	    TP_STRUCT__entry(

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