net: hisilicon: Add support for HI13X1 to hip04_eth (2ede8489) · Commits · 戴 / test

drivers/net/ethernet/hisilicon/Kconfig

+10 −0

Original line number	Diff line number	Diff line
		@@ -46,6 +46,16 @@ config HIP04_ETH
		If you wish to compile a kernel for a hardware with hisilicon p04 SoC and
		want to use the internal ethernet then you should answer Y to this.

		config HI13X1_GMAC
		bool "Hisilicon HI13X1 Network Device Support"
		depends on HIP04_ETH
		help
		If you wish to compile a kernel for a hardware with hisilicon hi13x1_gamc
		then you should answer Y to this. This makes this driver suitable for use
		on certain boards such as the HI13X1.

		If you are unsure, say N.

		config HNS_MDIO
		tristate
		select PHYLIB

drivers/net/ethernet/hisilicon/hip04_eth.c

+30 −7

Original line number	Diff line number	Diff line
		@@ -33,10 +33,23 @@
		#define GE_MODE_CHANGE_REG 0x1b4
		#define GE_RECV_CONTROL_REG 0x1e0
		#define GE_STATION_MAC_ADDRESS 0x210
		#define PPE_CFG_CPU_ADD_ADDR 0x580
		#define PPE_CFG_MAX_FRAME_LEN_REG 0x408

		#define PPE_CFG_BUS_CTRL_REG 0x424
		#define PPE_CFG_RX_CTRL_REG 0x428

		#if defined(CONFIG_HI13X1_GMAC)
		#define PPE_CFG_CPU_ADD_ADDR 0x6D0
		#define PPE_CFG_MAX_FRAME_LEN_REG 0x500
		#define PPE_CFG_RX_PKT_MODE_REG 0x504
		#define PPE_CFG_QOS_VMID_GEN 0x520
		#define PPE_CFG_RX_PKT_INT 0x740
		#define PPE_INTEN 0x700
		#define PPE_INTSTS 0x708
		#define PPE_RINT 0x704
		#define PPE_CFG_STS_MODE 0x880
		#else
		#define PPE_CFG_CPU_ADD_ADDR 0x580
		#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
		#define PPE_CFG_RX_PKT_MODE_REG 0x438
		#define PPE_CFG_QOS_VMID_GEN 0x500
		#define PPE_CFG_RX_PKT_INT 0x538
		@@ -44,6 +57,8 @@
		#define PPE_INTSTS 0x608
		#define PPE_RINT 0x604
		#define PPE_CFG_STS_MODE 0x700
		#endif /* CONFIG_HI13X1_GMAC */

		#define PPE_HIS_RX_PKT_CNT 0x804

		/* REG_INTERRUPT */
		@@ -93,18 +108,26 @@
		#define GE_RX_PORT_EN BIT(1)
		#define GE_TX_PORT_EN BIT(2)

		#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)

		#define PPE_CFG_RX_PKT_ALIGN BIT(18)
		#define PPE_CFG_QOS_VMID_MODE BIT(14)

		#if defined(CONFIG_HI13X1_GMAC)
		#define PPE_CFG_QOS_VMID_GRP_SHIFT 4
		#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 7
		#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(0)
		#define PPE_CFG_QOS_VMID_MODE BIT(15)
		#define PPE_CFG_BUS_LOCAL_REL (BIT(9) \| BIT(15) \| BIT(19) \| BIT(23))
		#else
		#define PPE_CFG_QOS_VMID_GRP_SHIFT 8
		#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
		#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)
		#define PPE_CFG_QOS_VMID_MODE BIT(14)
		#define PPE_CFG_BUS_LOCAL_REL BIT(14)
		#endif /* CONFIG_HI13X1_GMAC */

		#define PPE_CFG_RX_FIFO_FSFU BIT(11)
		#define PPE_CFG_RX_DEPTH_SHIFT 16
		#define PPE_CFG_RX_START_SHIFT 0
		#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11

		#define PPE_CFG_BUS_LOCAL_REL BIT(14)
		#define PPE_CFG_BUS_BIG_ENDIEN BIT(0)

		#define RX_DESC_NUM 128

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