Commit 2ed8e1f5 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Include "ignore lines" in skl+ wm state 



We'll need to poke at the "ignore lines" bit in the skl+
watermark registers for a w/a. Include that bit in the wm
state.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190213165424.22904-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
parent bfe0cd28

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -1126,6 +1126,7 @@ struct skl_wm_level { 
	u16 plane_res_b;

	u16 plane_res_b;

	u8 plane_res_l;

	u8 plane_res_l;

	bool plane_en;

	bool plane_en;

	bool ignore_lines;

};

};





/* Stores plane specific WM parameters */

/* Stores plane specific WM parameters */

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -6032,6 +6032,7 @@ enum { 
#define _CUR_WM_TRANS_A_0	0x70168

#define _CUR_WM_TRANS_A_0	0x70168

#define _CUR_WM_TRANS_B_0	0x71168

#define _CUR_WM_TRANS_B_0	0x71168

#define   PLANE_WM_EN		(1 << 31)

#define   PLANE_WM_EN		(1 << 31)

#define   PLANE_WM_IGNORE_LINES	(1 << 30)

#define   PLANE_WM_LINES_SHIFT	14

#define   PLANE_WM_LINES_SHIFT	14

#define   PLANE_WM_LINES_MASK	0x1f

#define   PLANE_WM_LINES_MASK	0x1f

#define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */

#define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */

drivers/gpu/drm/i915/intel_pm.c

+28 −16
Original line number Original line Diff line number Diff line
@@ -5053,11 +5053,12 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, 
{

{

	u32 val = 0;

	u32 val = 0;





	if (level->plane_en) {

	if (level->plane_en)

		val |= PLANE_WM_EN;

		val |= PLANE_WM_EN;

	if (level->ignore_lines)

		val |= PLANE_WM_IGNORE_LINES;

	val |= level->plane_res_b;

	val |= level->plane_res_b;

	val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;

	val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;

	}





	I915_WRITE_FW(reg, val);

	I915_WRITE_FW(reg, val);

}

}
@@ -5123,6 +5124,7 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1, 
			 const struct skl_wm_level *l2)

			 const struct skl_wm_level *l2)

{

{

	return l1->plane_en == l2->plane_en &&

	return l1->plane_en == l2->plane_en &&

		l1->ignore_lines == l2->ignore_lines &&

		l1->plane_res_l == l2->plane_res_l &&

		l1->plane_res_l == l2->plane_res_l &&

		l1->plane_res_b == l2->plane_res_b;

		l1->plane_res_b == l2->plane_res_b;

}

}
@@ -5331,19 +5333,28 @@ skl_print_wm_changes(struct intel_atomic_state *state) 
				      enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),

				      enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),

				      enast(new_wm->trans_wm.plane_en));

				      enast(new_wm->trans_wm.plane_en));





			DRM_DEBUG_KMS("[PLANE:%d:%s]   lines %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"

			DRM_DEBUG_KMS("[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"

				      " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",

				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",

				      plane->base.base.id, plane->base.name,

				      plane->base.base.id, plane->base.name,

				      old_wm->wm[0].plane_res_l, old_wm->wm[1].plane_res_l,

				      enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,

				      old_wm->wm[2].plane_res_l, old_wm->wm[3].plane_res_l,

				      enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,

				      old_wm->wm[4].plane_res_l, old_wm->wm[5].plane_res_l,

				      enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,

				      old_wm->wm[6].plane_res_l, old_wm->wm[7].plane_res_l,

				      enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,

				      old_wm->trans_wm.plane_res_l,

				      enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,

				      new_wm->wm[0].plane_res_l, new_wm->wm[1].plane_res_l,

				      enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,

				      new_wm->wm[2].plane_res_l, new_wm->wm[3].plane_res_l,

				      enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,

				      new_wm->wm[4].plane_res_l, new_wm->wm[5].plane_res_l,

				      enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,

				      new_wm->wm[6].plane_res_l, new_wm->wm[7].plane_res_l,

				      enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,

				      new_wm->trans_wm.plane_res_l);



				      enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,

				      enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,

				      enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,

				      enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,

				      enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,

				      enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,

				      enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,

				      enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,

				      enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);





			DRM_DEBUG_KMS("[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"

			DRM_DEBUG_KMS("[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"

				      " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",

				      " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5686,6 +5697,7 @@ static inline void skl_wm_level_from_reg_val(u32 val, 
					     struct skl_wm_level *level)

					     struct skl_wm_level *level)

{

{

	level->plane_en = val & PLANE_WM_EN;

	level->plane_en = val & PLANE_WM_EN;

	level->ignore_lines = val & PLANE_WM_IGNORE_LINES;

	level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;

	level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;

	level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &

	level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &

		PLANE_WM_LINES_MASK;

		PLANE_WM_LINES_MASK;

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