Commit 2ed5c2e3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v5.0/fixes-rc4' of... 

Merge tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

SoC fixes for omaps for v5.0-rc cycle

This series contains two SoC regression fixes and one uninitialized
variable fix:

- Fix inverted nirq pin handling for omap5 that started producing
  warnings with earlier GIC direction checks and took a while to
  understand and confirm. Basically there are two sys_nirq pins
  that are bypassing peripheral modules and inverted automatically
  by the SoC and need to be handled with a custom irq_set_type()

- Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
  code where the device tree handling code for timer source clock
  gets confused. It looks like we can remove that code eventually,
  but for now we just drop a bogus pm_runtime_irq_safe() for the
  timers with the related quirks caused by pm_runtime_irq_safe(),
  and have the standard assigned-clocks and assigned-clock-parents
  deal with setting the source clock

- Fix potentially uninitialized value for display init code if
  regmap_read() fails

* tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Variable "reg" in function omap4_dsi_mux_pads() could be uninitialized
  ARM: dts: Configure clock parent for pwm vibra
  bus: ti-sysc: Fix timer handling with drop pm_runtime_irq_safe()
  ARM: OMAP5+: Fix inverted nirq pin interrupts with irq_set_type
  clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparenting
parents d1393711 dc30e703

arch/arm/boot/dts/omap4-droid4-xt894.dts

+11 −0
Original line number Diff line number Diff line
@@ -644,6 +644,17 @@ 
	};

};



/* Configure pwm clock source for timers 8 & 9 */

&timer8 {

	assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;

	assigned-clock-parents = <&sys_clkin_ck>;

};



&timer9 {

	assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;

	assigned-clock-parents = <&sys_clkin_ck>;

};



/*

 * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for

 * uart1 wakeirq.

arch/arm/boot/dts/omap5-board-common.dtsi

+6 −3
Original line number Diff line number Diff line
@@ -317,7 +317,8 @@ 


	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {

		pinctrl-single,pins = <

			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */

			/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */

			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)

		>;

	};
@@ -385,7 +386,8 @@ 


	palmas: palmas@48 {

		compatible = "ti,palmas";

		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */

		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */

		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;

		reg = <0x48>;

		interrupt-controller;

		#interrupt-cells = <2>;
@@ -651,7 +653,8 @@ 
		pinctrl-names = "default";

		pinctrl-0 = <&twl6040_pins>;



		interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */

		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */

		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;



		/* audpwron gpio defined in the board specific dts */

arch/arm/boot/dts/omap5-cm-t54.dts

+11 −1
Original line number Diff line number Diff line
@@ -181,6 +181,13 @@ 
			OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6)  /* llib_wakereqin.gpio1_wk15 */

		>;

	};



	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {

		pinctrl-single,pins = <

			/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */

			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)

		>;

	};

};



&omap5_pmx_core {
@@ -414,8 +421,11 @@ 


	palmas: palmas@48 {

		compatible = "ti,palmas";

		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */

		reg = <0x48>;

		pinctrl-0 = <&palmas_sys_nirq_pins>;

		pinctrl-names = "default";

		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */

		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;

		interrupt-controller;

		#interrupt-cells = <2>;

		ti,system-power-controller;

arch/arm/mach-omap2/display.c

+6 −1
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 
	u32 enable_mask, enable_shift;

	u32 pipd_mask, pipd_shift;

	u32 reg;

	int ret;



	if (dsi_id == 0) {

		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
@@ -98,7 +99,11 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 
		return -ENODEV;

	}



	regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);

	ret = regmap_read(omap4_dsi_mux_syscon,

					  OMAP4_DSIPHY_SYSCON_OFFSET,

					  &reg);

	if (ret)

		return ret;



	reg &= ~enable_mask;

	reg &= ~pipd_mask;

arch/arm/mach-omap2/omap-wakeupgen.c

+35 −1
Original line number Diff line number Diff line
@@ -50,6 +50,9 @@ 
#define OMAP4_NR_BANKS		4

#define OMAP4_NR_IRQS		128



#define SYS_NIRQ1_EXT_SYS_IRQ_1	7

#define SYS_NIRQ2_EXT_SYS_IRQ_2	119



static void __iomem *wakeupgen_base;

static void __iomem *sar_base;

static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
@@ -153,6 +156,37 @@ static void wakeupgen_unmask(struct irq_data *d) 
	irq_chip_unmask_parent(d);

}



/*

 * The sys_nirq pins bypass peripheral modules and are wired directly

 * to MPUSS wakeupgen. They get automatically inverted for GIC.

 */

static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)

{

	bool inverted = false;



	switch (type) {

	case IRQ_TYPE_LEVEL_LOW:

		type &= ~IRQ_TYPE_LEVEL_MASK;

		type |= IRQ_TYPE_LEVEL_HIGH;

		inverted = true;

		break;

	case IRQ_TYPE_EDGE_FALLING:

		type &= ~IRQ_TYPE_EDGE_BOTH;

		type |= IRQ_TYPE_EDGE_RISING;

		inverted = true;

		break;

	default:

		break;

	}



	if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&

	    d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)

		pr_warn("wakeupgen: irq%li polarity inverted in dts\n",

			d->hwirq);



	return irq_chip_set_type_parent(d, type);

}



#ifdef CONFIG_HOTPLUG_CPU

static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
@@ -446,7 +480,7 @@ static struct irq_chip wakeupgen_chip = { 
	.irq_mask		= wakeupgen_mask,

	.irq_unmask		= wakeupgen_unmask,

	.irq_retrigger		= irq_chip_retrigger_hierarchy,

	.irq_set_type		= irq_chip_set_type_parent,

	.irq_set_type		= wakeupgen_irq_set_type,

	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,

#ifdef CONFIG_SMP

	.irq_set_affinity	= irq_chip_set_affinity_parent,

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