Commit 2ec35a42 authored by Tomasz Figa's avatar Tomasz Figa Committed by Kukjin Kim
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ARM: dts: Add dts file for S3C6410-based SMDK6410 board



This patch adds basic device tree sources for SAMSUNG SMDK6410 board
based on SAMSUNG S3C6410 SoC.

Currently only UARTs, SD channel 0 and 100Mbps ethernet (SMSC911x) are
supported.

Signed-off-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent a43736de
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+2 −1
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@@ -194,7 +194,8 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
	ste-ccu8540.dtb \
	ste-ccu9540.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
	s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
	emev2-kzm9d-reference.dtb \
	r8a7740-armadillo800eva.dtb \
+103 −0
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/*
 * Samsung S3C6410 based SMDK6410 board device tree source.
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Device tree source file for SAMSUNG SMDK6410 board which is based on
 * Samsung's S3C6410 SoC.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "s3c6410.dtsi"

/ {
	model = "SAMSUNG SMDK6410 board based on S3C6410";
	compatible = "samsung,mini6410", "samsung,s3c6410";

	memory {
		reg = <0x50000000 0x8000000>;
	};

	chosen {
		bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		fin_pll: oscillator@0 {
			compatible = "fixed-clock";
			reg = <0>;
			clock-frequency = <12000000>;
			clock-output-names = "fin_pll";
			#clock-cells = <0>;
		};

		xusbxti: oscillator@1 {
			compatible = "fixed-clock";
			reg = <1>;
			clock-output-names = "xusbxti";
			clock-frequency = <48000000>;
			#clock-cells = <0>;
		};
	};

	srom-cs1@18000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x18000000 0x8000000>;
		ranges;

		ethernet@18000000 {
			compatible = "smsc,lan9115";
			reg = <0x18000000 0x10000>;
			interrupt-parent = <&gpn>;
			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
			phy-mode = "mii";
			reg-io-width = <4>;
			smsc,force-internal-phy;
		};
	};
};

&sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
	bus-width = <4>;
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_data>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_data>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_data>;
	status = "okay";
};