Commit 2ec1e4b4 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
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arm64: dts: renesas: r8a77980: add SMP support 



Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
delivery masks for the ARM GIC and Architectured Timer.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: default avatarVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
[simon: corrected whitespace]
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 1b1b30a2

arch/arm64/boot/dts/renesas/r8a77980.dtsi

+35 −5
Original line number Diff line number Diff line
@@ -30,6 +30,36 @@ 
			enable-method = "psci";

		};



		a53_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <1>;

			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;

			power-domains = <&sysc R8A77980_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		a53_2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <2>;

			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;

			power-domains = <&sysc R8A77980_PD_CA53_CPU2>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		a53_3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <3>;

			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;

			power-domains = <&sysc R8A77980_PD_CA53_CPU3>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		L2_CA53: cache-controller {

			compatible = "cache";

			power-domains = <&sysc R8A77980_PD_CA53_SCU>;
@@ -408,7 +438,7 @@ 
			      <0x0 0xf1020000 0 0x20000>,

			      <0x0 0xf1040000 0 0x20000>,

			      <0x0 0xf1060000 0 0x20000>;

			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |

			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(4) |

				      IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&cpg CPG_MOD 408>;

			clock-names = "clk";
@@ -424,13 +454,13 @@ 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |

				       IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |

				       IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |

				       IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |

				       IRQ_TYPE_LEVEL_LOW)>;

	};

};

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