Unverified Commit 2e927ad7 authored by David Lin's avatar David Lin Committed by Mark Brown
Browse files

ASoC: nau8822: support master mode 



The driver selects the proper BCLK divide through the BCLK and FS
at the hardware parameter when the I2S master mode.

Signed-off-by: default avatarDavid Lin <CTLIN0@nuvoton.com>
Signed-off-by: default avatarJohn Hsu <KCHSU0@nuvoton.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 960f428c

sound/soc/codecs/nau8822.c

+18 −0
Original line number Diff line number Diff line
@@ -828,6 +828,24 @@ static int nau8822_hw_params(struct snd_pcm_substream *substream, 
	struct snd_soc_component *component = dai->component;

	struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);

	int val_len = 0, val_rate = 0;

	unsigned int ctrl_val, bclk_fs, bclk_div;



	/* make BCLK and LRC divide configuration if the codec as master. */

	snd_soc_component_read(component, NAU8822_REG_CLOCKING, &ctrl_val);

	if (ctrl_val & NAU8822_CLK_MASTER) {

		/* get the bclk and fs ratio */

		bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);

		if (bclk_fs <= 32)

			bclk_div = NAU8822_BCLKDIV_8;

		else if (bclk_fs <= 64)

			bclk_div = NAU8822_BCLKDIV_4;

		else if (bclk_fs <= 128)

			bclk_div = NAU8822_BCLKDIV_2;

		else

			return -EINVAL;

		snd_soc_component_update_bits(component, NAU8822_REG_CLOCKING,

				NAU8822_BCLKSEL_MASK, bclk_div);

	}



	switch (params_format(params)) {

	case SNDRV_PCM_FORMAT_S16_LE:

sound/soc/codecs/nau8822.h

+7 −0
Original line number Diff line number Diff line
@@ -107,10 +107,17 @@ 


/* NAU8822_REG_CLOCKING (0x6) */

#define NAU8822_CLKIOEN_MASK			0x1

#define NAU8822_CLK_MASTER			0x1

#define NAU8822_CLK_SLAVE			0x0

#define NAU8822_MCLKSEL_SFT			5

#define NAU8822_MCLKSEL_MASK			(0x7 << 5)

#define NAU8822_BCLKSEL_SFT			2

#define NAU8822_BCLKSEL_MASK			(0x7 << 2)

#define NAU8822_BCLKDIV_1			(0x0 << 2)

#define NAU8822_BCLKDIV_2			(0x1 << 2)

#define NAU8822_BCLKDIV_4			(0x2 << 2)

#define NAU8822_BCLKDIV_8			(0x3 << 2)

#define NAU8822_BCLKDIV_16			(0x4 << 2)

#define NAU8822_CLKM_MASK			(0x1 << 8)

#define NAU8822_CLKM_MCLK			(0x0 << 8)

#define NAU8822_CLKM_PLL			(0x1 << 8)

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