drm/nouveau/flcn/cmdq: split the condition for queue readiness vs pmu acr readiness (2e8a6597) · Commits · 戴 / test

drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -15,6 +15,8 @@ struct nvkm_pmu {
	struct nvkm_falcon_msgq *msgq;		struct nvkm_falcon_msgq *msgq;
	struct nvkm_msgqueue *queue;		struct nvkm_msgqueue *queue;

			struct completion wpr_ready;

	struct {		struct {
	u32 base;		u32 base;
	u32 size;		u32 size;

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

+9 −4

Original line number	Original line	Diff line number	Diff line
	@@ -156,14 +156,16 @@ nvkm_msgqueue_post(struct nvkm_msgqueue *priv, enum msgqueue_msg_priority prio,
	struct nvkm_msgqueue_queue *queue;		struct nvkm_msgqueue_queue *queue;
	int ret;		int ret;

	if (wait_init && !wait_for_completion_timeout(&priv->init_done,
	msecs_to_jiffies(1000)))
	return -ETIMEDOUT;

	queue = priv->func->cmd_queue(priv, prio);		queue = priv->func->cmd_queue(priv, prio);
	if (IS_ERR(queue))		if (IS_ERR(queue))
	return PTR_ERR(queue);		return PTR_ERR(queue);

			if (!wait_for_completion_timeout(&queue->ready,
			msecs_to_jiffies(1000))) {
			FLCNQ_ERR(queue, "timeout waiting for queue ready");
			return -ETIMEDOUT;
			}

	seq = nvkm_falcon_qmgr_seq_acquire(queue->qmgr);		seq = nvkm_falcon_qmgr_seq_acquire(queue->qmgr);
	if (IS_ERR(seq))		if (IS_ERR(seq))
	return PTR_ERR(seq);		return PTR_ERR(seq);
	@@ -197,6 +199,7 @@ nvkm_msgqueue_post(struct nvkm_msgqueue *priv, enum msgqueue_msg_priority prio,
	void		void
	nvkm_falcon_cmdq_fini(struct nvkm_falcon_cmdq *cmdq)		nvkm_falcon_cmdq_fini(struct nvkm_falcon_cmdq *cmdq)
	{		{
			reinit_completion(&cmdq->ready);
	}		}

	void		void
	@@ -209,6 +212,7 @@ nvkm_falcon_cmdq_init(struct nvkm_falcon_cmdq *cmdq,
	cmdq->tail_reg = func->cmdq.tail + index * func->cmdq.stride;		cmdq->tail_reg = func->cmdq.tail + index * func->cmdq.stride;
	cmdq->offset = offset;		cmdq->offset = offset;
	cmdq->size = size;		cmdq->size = size;
			complete_all(&cmdq->ready);

	FLCNQ_DBG(cmdq, "initialised @ index %d offset 0x%08x size 0x%08x",		FLCNQ_DBG(cmdq, "initialised @ index %d offset 0x%08x size 0x%08x",
	index, cmdq->offset, cmdq->size);		index, cmdq->offset, cmdq->size);
	@@ -236,5 +240,6 @@ nvkm_falcon_cmdq_new(struct nvkm_falcon_qmgr qmgr, const char name,
	cmdq->qmgr = qmgr;		cmdq->qmgr = qmgr;
	cmdq->name = name;		cmdq->name = name;
	mutex_init(&cmdq->mutex);		mutex_init(&cmdq->mutex);
			init_completion(&cmdq->ready);
	return 0;		return 0;
	}		}

drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c

+0 −6

Original line number	Original line	Diff line number	Diff line
	@@ -126,8 +126,6 @@ nvkm_msgqueue_reinit(struct nvkm_msgqueue *queue)
	return 0;		return 0;

	queue->init_msg_received = false;		queue->init_msg_received = false;
	reinit_completion(&queue->init_done);

	return 0;		return 0;
	}		}

	@@ -138,8 +136,4 @@ nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func *func,
	{		{
	queue->func = func;		queue->func = func;
	queue->falcon = falcon;		queue->falcon = falcon;

	init_completion(&queue->init_done);


	}		}

drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -140,6 +140,8 @@ struct nvkm_msgqueue_queue {

	u32 head_reg;		u32 head_reg;
	u32 tail_reg;		u32 tail_reg;

			struct completion ready;
	};		};

	/**		/**
	@@ -148,14 +150,12 @@ struct nvkm_msgqueue_queue {
	* @falcon: falcon to be managed		* @falcon: falcon to be managed
	* @func: implementation of the firmware to use		* @func: implementation of the firmware to use
	* @init_msg_received: whether the init message has already been received		* @init_msg_received: whether the init message has already been received
	* @init_done: whether all init is complete and commands can be processed
	*/		*/
	struct nvkm_msgqueue {		struct nvkm_msgqueue {
	struct nvkm_falcon *falcon;		struct nvkm_falcon *falcon;
	const struct nvkm_msgqueue_func *func;		const struct nvkm_msgqueue_func *func;
	u32 fw_version;		u32 fw_version;
	bool init_msg_received;		bool init_msg_received;
	struct completion init_done;
	};		};

	void nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func , struct nvkm_falcon ,		void nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func , struct nvkm_falcon ,

drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c

+15 −1

Original line number	Original line	Diff line number	Diff line
	@@ -187,7 +187,7 @@ acr_init_wpr_callback(void priv, struct nv_falcon_msg hdr)
	}		}

	nvkm_debug(subdev, "ACR WPR init complete\n");		nvkm_debug(subdev, "ACR WPR init complete\n");
	complete_all(&queue->init_done);		complete_all(&subdev->device->pmu->wpr_ready);
	return 0;		return 0;
	}		}

	@@ -246,6 +246,7 @@ enum {
	static int		static int
	acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon)		acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon)
	{		{
			struct nvkm_pmu *pmu = priv->falcon->owner->device->pmu;
	DECLARE_COMPLETION_ONSTACK(completed);		DECLARE_COMPLETION_ONSTACK(completed);
	/*		/*
	* flags - Flag specifying RESET or no RESET.		* flags - Flag specifying RESET or no RESET.
	@@ -258,6 +259,12 @@ acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon)
	u32 falcon_id;		u32 falcon_id;
	} cmd;		} cmd;

			if (!wait_for_completion_timeout(&pmu->wpr_ready,
			msecs_to_jiffies(1000))) {
			nvkm_error(&pmu->subdev, "timeout waiting for WPR init\n");
			return -ETIMEDOUT;
			}

	memset(&cmd, 0, sizeof(cmd));		memset(&cmd, 0, sizeof(cmd));

	cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;		cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;
	@@ -301,6 +308,7 @@ acr_boot_multiple_falcons_callback(void _priv, struct nv_falcon_msg hdr)
	static int		static int
	acr_boot_multiple_falcons(struct nvkm_msgqueue *priv, unsigned long falcon_mask)		acr_boot_multiple_falcons(struct nvkm_msgqueue *priv, unsigned long falcon_mask)
	{		{
			struct nvkm_pmu *pmu = priv->falcon->owner->device->pmu;
	DECLARE_COMPLETION_ONSTACK(completed);		DECLARE_COMPLETION_ONSTACK(completed);
	/*		/*
	* flags - Flag specifying RESET or no RESET.		* flags - Flag specifying RESET or no RESET.
	@@ -317,6 +325,12 @@ acr_boot_multiple_falcons(struct nvkm_msgqueue *priv, unsigned long falcon_mask)
	} cmd;		} cmd;
	struct msgqueue_0137bca5 *queue = msgqueue_0137bca5(priv);		struct msgqueue_0137bca5 *queue = msgqueue_0137bca5(priv);

			if (!wait_for_completion_timeout(&pmu->wpr_ready,
			msecs_to_jiffies(1000))) {
			nvkm_error(&pmu->subdev, "timeout waiting for WPR init\n");
			return -ETIMEDOUT;
			}

	memset(&cmd, 0, sizeof(cmd));		memset(&cmd, 0, sizeof(cmd));

	cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;		cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR;

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