Commit 2e28f3b1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-5.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:
 "A smattering of fixes and cleanups:

   - Dead code removal.

   - Exporting riscv_cpuid_to_hartid_mask for modules.

   - Per-CPU tracking of ISA features.

   - Setting max_pfn correctly when probing memory.

   - Adding a note to the VDSO so glibc can check the kernel's version
     without a uname().

   - A fix to force the bootloader to initialize the boot spin tables,
     which still get used as a fallback when SBI-0.1 is enabled"

* tag 'riscv-for-linus-5.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  RISC-V: Remove unused code from STRICT_KERNEL_RWX
  riscv: force __cpu_up_ variables to put in data section
  riscv: add Linux note to vdso
  riscv: set max_pfn to the PFN of the last page
  RISC-V: Remove N-extension related defines
  RISC-V: Add bitmap reprensenting ISA features common across CPUs
  RISC-V: Export riscv_cpuid_to_hartid_mask() API
parents 1a263ae6 73cb8e2a

arch/riscv/include/asm/csr.h

+0 −3
Original line number Diff line number Diff line
@@ -51,13 +51,10 @@ 
#define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))



/* Interrupt causes (minus the high bit) */

#define IRQ_U_SOFT		0

#define IRQ_S_SOFT		1

#define IRQ_M_SOFT		3

#define IRQ_U_TIMER		4

#define IRQ_S_TIMER		5

#define IRQ_M_TIMER		7

#define IRQ_U_EXT		8

#define IRQ_S_EXT		9

#define IRQ_M_EXT		11

arch/riscv/include/asm/hwcap.h

+22 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#ifndef _ASM_RISCV_HWCAP_H

#define _ASM_RISCV_HWCAP_H



#include <linux/bits.h>

#include <uapi/asm/hwcap.h>



#ifndef __ASSEMBLY__
@@ -22,6 +23,27 @@ enum { 
};



extern unsigned long elf_hwcap;



#define RISCV_ISA_EXT_a		('a' - 'a')

#define RISCV_ISA_EXT_c		('c' - 'a')

#define RISCV_ISA_EXT_d		('d' - 'a')

#define RISCV_ISA_EXT_f		('f' - 'a')

#define RISCV_ISA_EXT_h		('h' - 'a')

#define RISCV_ISA_EXT_i		('i' - 'a')

#define RISCV_ISA_EXT_m		('m' - 'a')

#define RISCV_ISA_EXT_s		('s' - 'a')

#define RISCV_ISA_EXT_u		('u' - 'a')



#define RISCV_ISA_EXT_MAX	64



unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);



#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)



bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);

#define riscv_isa_extension_available(isa_bitmap, ext)	\

	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)



#endif



#endif /* _ASM_RISCV_HWCAP_H */

arch/riscv/include/asm/set_memory.h

+0 −8
Original line number Diff line number Diff line
@@ -22,14 +22,6 @@ static inline int set_memory_x(unsigned long addr, int numpages) { return 0; } 
static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }

#endif



#ifdef CONFIG_STRICT_KERNEL_RWX

void set_kernel_text_ro(void);

void set_kernel_text_rw(void);

#else

static inline void set_kernel_text_ro(void) { }

static inline void set_kernel_text_rw(void) { }

#endif



int set_direct_map_invalid_noflush(struct page *page);

int set_direct_map_default_noflush(struct page *page);

arch/riscv/kernel/cpu_ops.c

+2 −2
Original line number Diff line number Diff line
@@ -15,8 +15,8 @@ 


const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;



void *__cpu_up_stack_pointer[NR_CPUS];

void *__cpu_up_task_pointer[NR_CPUS];

void *__cpu_up_stack_pointer[NR_CPUS] __section(.data);

void *__cpu_up_task_pointer[NR_CPUS] __section(.data);



extern const struct cpu_operations cpu_ops_sbi;

extern const struct cpu_operations cpu_ops_spinwait;

arch/riscv/kernel/cpufeature.c

+80 −3
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 * Copyright (C) 2017 SiFive

 */



#include <linux/bitmap.h>

#include <linux/of.h>

#include <asm/processor.h>

#include <asm/hwcap.h>
@@ -13,15 +14,57 @@ 
#include <asm/switch_to.h>



unsigned long elf_hwcap __read_mostly;



/* Host ISA bitmap */

static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;



#ifdef CONFIG_FPU

bool has_fpu __read_mostly;

#endif



/**

 * riscv_isa_extension_base() - Get base extension word

 *

 * @isa_bitmap: ISA bitmap to use

 * Return: base extension word as unsigned long value

 *

 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.

 */

unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)

{

	if (!isa_bitmap)

		return riscv_isa[0];

	return isa_bitmap[0];

}

EXPORT_SYMBOL_GPL(riscv_isa_extension_base);



/**

 * __riscv_isa_extension_available() - Check whether given extension

 * is available or not

 *

 * @isa_bitmap: ISA bitmap to use

 * @bit: bit position of the desired extension

 * Return: true or false

 *

 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.

 */

bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)

{

	const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;



	if (bit >= RISCV_ISA_EXT_MAX)

		return false;



	return test_bit(bit, bmap) ? true : false;

}

EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);



void riscv_fill_hwcap(void)

{

	struct device_node *node;

	const char *isa;

	size_t i;

	char print_str[BITS_PER_LONG + 1];

	size_t i, j, isa_len;

	static unsigned long isa2hwcap[256] = {0};



	isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
@@ -33,8 +76,11 @@ void riscv_fill_hwcap(void) 


	elf_hwcap = 0;



	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);



	for_each_of_cpu_node(node) {

		unsigned long this_hwcap = 0;

		unsigned long this_isa = 0;



		if (riscv_of_processor_hartid(node) < 0)

			continue;
@@ -44,8 +90,24 @@ void riscv_fill_hwcap(void) 
			continue;

		}



		for (i = 0; i < strlen(isa); ++i)

		i = 0;

		isa_len = strlen(isa);

#if IS_ENABLED(CONFIG_32BIT)

		if (!strncmp(isa, "rv32", 4))

			i += 4;

#elif IS_ENABLED(CONFIG_64BIT)

		if (!strncmp(isa, "rv64", 4))

			i += 4;

#endif

		for (; i < isa_len; ++i) {

			this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];

			/*

			 * TODO: X, Y and Z extension parsing for Host ISA

			 * bitmap will be added in-future.

			 */

			if ('a' <= isa[i] && isa[i] < 'x')

				this_isa |= (1UL << (isa[i] - 'a'));

		}



		/*

		 * All "okay" hart should have same isa. Set HWCAP based on
@@ -56,6 +118,11 @@ void riscv_fill_hwcap(void) 
			elf_hwcap &= this_hwcap;

		else

			elf_hwcap = this_hwcap;



		if (riscv_isa[0])

			riscv_isa[0] &= this_isa;

		else

			riscv_isa[0] = this_isa;

	}



	/* We don't support systems with F but without D, so mask those out
@@ -65,7 +132,17 @@ void riscv_fill_hwcap(void) 
		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;

	}



	pr_info("elf_hwcap is 0x%lx\n", elf_hwcap);

	memset(print_str, 0, sizeof(print_str));

	for (i = 0, j = 0; i < BITS_PER_LONG; i++)

		if (riscv_isa[0] & BIT_MASK(i))

			print_str[j++] = (char)('a' + i);

	pr_info("riscv: ISA extensions %s\n", print_str);



	memset(print_str, 0, sizeof(print_str));

	for (i = 0, j = 0; i < BITS_PER_LONG; i++)

		if (elf_hwcap & BIT_MASK(i))

			print_str[j++] = (char)('a' + i);

	pr_info("riscv: ELF capabilities %s\n", print_str);



#ifdef CONFIG_FPU

	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))

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