net: dp83869: Fix RGMII internal delay configuration (2e1ec861) · Commits · 戴 / test

The RGMII control register at 0x32 indicates the states for the bits RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: RGMII Transmit/Receive Clock Delay 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. This commit fixes the inversed behavior of these bits Fixes: ("net: dp83869: Add RGMII internal delay configuration") Signed-off-by:

Daniel Gorsulowski <daniel.gorsulowski@esd.eu> Acked-by:

Dan Murphy <dmurphy@ti.com> Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/phy/dp83869.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -427,18 +427,18 @@ static int dp83869_config_init(struct phy_device *phydev)
		return ret;

		val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
		val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN \|
		val \|= (DP83869_RGMII_TX_CLK_DELAY_EN \|
		DP83869_RGMII_RX_CLK_DELAY_EN);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
		val \|= (DP83869_RGMII_TX_CLK_DELAY_EN \|
		val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN \|
		DP83869_RGMII_RX_CLK_DELAY_EN);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
		val \|= DP83869_RGMII_TX_CLK_DELAY_EN;
		val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
		val \|= DP83869_RGMII_RX_CLK_DELAY_EN;
		val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;

		ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
		val);

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