drm/radeon: add helper function to support golden registers (2e1b65f9) · Commits · 戴 / test

drivers/gpu/drm/radeon/radeon.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -1946,6 +1946,9 @@ extern void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc
		extern int radeon_resume_kms(struct drm_device *dev);
		extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
		extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
		extern void radeon_program_register_sequence(struct radeon_device *rdev,
		const u32 *registers,
		const u32 array_size);

		/*
		* vm

+36 −0

Original line number	Diff line number	Diff line
		@@ -97,6 +97,42 @@ static const char radeon_family_name[][16] = {
		"LAST",
		};

		/**
		* radeon_program_register_sequence - program an array of registers.
		*
		* @rdev: radeon_device pointer
		* @registers: pointer to the register array
		* @array_size: size of the register array
		*
		* Programs an array or registers with and and or masks.
		* This is a helper for setting golden registers.
		*/
		void radeon_program_register_sequence(struct radeon_device *rdev,
		const u32 *registers,
		const u32 array_size)
		{
		u32 tmp, reg, and_mask, or_mask;
		int i;

		if (array_size % 3)
		return;

		for (i = 0; i < array_size; i +=3) {
		reg = registers[i + 0];
		and_mask = registers[i + 1];
		or_mask = registers[i + 2];

		if (and_mask == 0xffffffff) {
		tmp = or_mask;
		} else {
		tmp = RREG32(reg);
		tmp &= ~and_mask;
		tmp \|= or_mask;
		}
		WREG32(reg, tmp);
		}
		}

		/**
		* radeon_surface_init - Clear GPU surface registers.
		*