Commit 2e19af94 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/tgl: Wa_1409600907 



To avoid possible hang, we need to add depth stall if we flush the
depth cache.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-8-mika.kuoppala@linux.intel.com
parent 2cbe2d8c

drivers/gpu/drm/i915/gt/intel_lrc.c

+4 −0
Original line number Diff line number Diff line
@@ -3203,6 +3203,8 @@ static int gen12_emit_flush_render(struct i915_request *request, 
		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		/* Wa_1409600907:tgl */

		flags |= PIPE_CONTROL_DEPTH_STALL;

		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
@@ -3435,6 +3437,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 
				      PIPE_CONTROL_TILE_CACHE_FLUSH |

				      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

				      PIPE_CONTROL_DEPTH_CACHE_FLUSH |

				      /* Wa_1409600907:tgl */

				      PIPE_CONTROL_DEPTH_STALL |

				      PIPE_CONTROL_DC_FLUSH_ENABLE |

				      PIPE_CONTROL_FLUSH_ENABLE |

				      PIPE_CONTROL_HDC_PIPELINE_FLUSH);

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