Commit 2e113c64 authored by Vaibhav Hiremath's avatar Vaibhav Hiremath Committed by Paul Walmsley
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ARM: OMAP2+: control: Add AM33XX control reg & sec clkctrl offset 



Define AM33XX control register, in order to allow access to
control register address space, also add CONTROL_SEC_CLK_CTRL
register offset; both are required in clock tree data,
for wdt0 and timer0 clock source select configuration.

CONTROL.SEC_CLK_CTRL register is provided to select/configure
clock input for WDT0 and TIMER0.

Signed-off-by: default avatarVaibhav Hiremath <hvaibhav@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: added include of plat/am33xx.h to fix build break;
 added AM33XX_CONTROL_STATUS bitfields that will be needed for the clock
 tree; fixed some control.h whitespace problems while here]
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 08f30989

arch/arm/mach-omap2/control.h

+23 −16
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#include <mach/ctrl_module_pad_core_44xx.h>

#include <mach/ctrl_module_pad_wkup_44xx.h>



#include <plat/am33xx.h>



#ifndef __ASSEMBLY__

#define OMAP242X_CTRL_REGADDR(reg)					\

		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -28,6 +30,8 @@ 
		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))

#define OMAP343X_CTRL_REGADDR(reg)					\

		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))

#define AM33XX_CTRL_REGADDR(reg)					\

		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))

#else

#define OMAP242X_CTRL_REGADDR(reg)					\

		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +39,8 @@ 
		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))

#define OMAP343X_CTRL_REGADDR(reg)					\

		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))

#define AM33XX_CTRL_REGADDR(reg)					\

		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))

#endif /* __ASSEMBLY__ */



/*
@@ -337,14 +343,15 @@ 
#define AM35XX_HECC_SW_RST		BIT(3)

#define AM35XX_VPFE_PCLK_SW_RST		BIT(4)



/*

 * CONTROL AM33XX STATUS register

 */

/* AM33XX CONTROL_STATUS register */

#define AM33XX_CONTROL_STATUS		0x040

#define AM33XX_CONTROL_SEC_CLK_CTRL	0x1bc



/*

 * CONTROL OMAP STATUS register to identify OMAP3 features

 */

/* AM33XX CONTROL_STATUS bitfields (partial) */

#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT		22

#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)



/* CONTROL OMAP STATUS register to identify OMAP3 features */

#define OMAP3_CONTROL_OMAP_STATUS	0x044c



#define OMAP3_SGX_SHIFT			13

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