Commit 2e0cc4d4 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu: revise RLCG access path 



what changed:
1)provide new implementation interface for the rlcg access path
2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op
function can access reg that need RLCG path help

now even debugfs's reg_op can used to dump wave.

tested-by: default avatarMonk Liu <monk.liu@amd.com>
tested-by: default avatarZhou pengju <pengju.zhou@amd.com>
Signed-off-by: default avatarZhou pengju <pengju.zhou@amd.com>
Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarEmily Deng <Emily.Deng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a7fbb630

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0
Original line number Diff line number Diff line
@@ -994,6 +994,8 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 
			uint32_t acc_flags);

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags);

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags);

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 
		} else {

			r = get_user(value, (uint32_t *)buf);

			if (!r)

				WREG32(*pos >> 2, value);

				amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value, 0);

		}

		if (r) {

			result = r;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+37 −13
Original line number Diff line number Diff line
@@ -306,6 +306,26 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) 
		BUG();

}



void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t acc_flags)

{

	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);



	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))

		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));

	else {

		unsigned long flags;



		spin_lock_irqsave(&adev->mmio_idx_lock, flags);

		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));

		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));

		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);

	}



	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {

		udelay(500);

	}

}



/**

 * amdgpu_mm_wreg - write to a memory mapped IO register

 *
@@ -319,8 +339,6 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) 
void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags)

{

	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);



	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {

		adev->last_mm_index = v;

	}
@@ -328,20 +346,26 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 
	if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))

		return amdgpu_kiq_wreg(adev, reg, v);



	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))

		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));

	else {

		unsigned long flags;



		spin_lock_irqsave(&adev->mmio_idx_lock, flags);

		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));

		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));

		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);

	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);

}



	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {

		udelay(500);

/*

 * amdgpu_mm_wreg_mmio_rlc -  write register either with mmio or with RLC path if in range

 *

 * this function is invoked only the debugfs register access

 * */

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags)

{

	if (amdgpu_sriov_fullaccess(adev) &&

		adev->gfx.rlc.funcs &&

		adev->gfx.rlc.funcs->is_rlcg_access_range) {



		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))

			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);

	}



	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

+2 −0
Original line number Diff line number Diff line
@@ -127,6 +127,8 @@ struct amdgpu_rlc_funcs { 
	void (*reset)(struct amdgpu_device *adev);

	void (*start)(struct amdgpu_device *adev);

	void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);

	void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v);

	bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);

};



struct amdgpu_rlc {

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+3 −0
Original line number Diff line number Diff line
@@ -270,6 +270,9 @@ struct amdgpu_virt { 
#define amdgpu_sriov_runtime(adev) \

((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)



#define amdgpu_sriov_fullaccess(adev) \

(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))



#define amdgpu_passthrough(adev) \

((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)

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