Commit 2dcabf05 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
Browse files

clk: tegra: Mark HCLK, SCLK and EMC as critical 



Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
as critical.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Cc: <stable@vger.kernel.org> # v4.16
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent e403d005

drivers/clk/tegra/clk-emc.c

+1 −1
Original line number Diff line number Diff line
@@ -515,7 +515,7 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 


	init.name = "emc";

	init.ops = &tegra_clk_emc_ops;

	init.flags = 0;

	init.flags = CLK_IS_CRITICAL;

	init.parent_names = emc_parent_clk_names;

	init.num_parents = ARRAY_SIZE(emc_parent_clk_names);

drivers/clk/tegra/clk-tegra-periph.c

+1 −1
Original line number Diff line number Diff line
@@ -830,7 +830,7 @@ static struct tegra_periph_init_data gate_clks[] = { 
	GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),

	GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),

	GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),

	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),

	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),

	GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),

	GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),

	GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),

drivers/clk/tegra/clk-tegra-super-gen4.c

+5 −3
Original line number Diff line number Diff line
@@ -125,7 +125,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
		/* SCLK */

		dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);

		if (dt_clk) {

			clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,

			clk = clk_register_divider(NULL, "sclk", "sclk_mux",

						CLK_IS_CRITICAL,

						clk_base + SCLK_DIVIDER, 0, 8,

						0, &sysrate_lock);

			*dt_clk = clk;
@@ -137,7 +138,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
			clk = tegra_clk_register_super_mux("sclk",

						gen_info->sclk_parents,

						gen_info->num_sclk_parents,

						CLK_SET_RATE_PARENT,

						CLK_SET_RATE_PARENT |

						CLK_IS_CRITICAL,

						clk_base + SCLK_BURST_POLICY,

						0, 4, 0, 0, NULL);

			*dt_clk = clk;
@@ -151,7 +153,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
				   clk_base + SYSTEM_CLK_RATE, 4, 2, 0,

				   &sysrate_lock);

		clk = clk_register_gate(NULL, "hclk", "hclk_div",

				CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,

				CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

				clk_base + SYSTEM_CLK_RATE,

				7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);

		*dt_clk = clk;

drivers/clk/tegra/clk-tegra114.c

+1 −2
Original line number Diff line number Diff line
@@ -955,8 +955,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, 


	/* PLLM */

	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,

			     CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,

			     &pll_m_params, NULL);

			     CLK_SET_RATE_GATE, &pll_m_params, NULL);

	clks[TEGRA114_CLK_PLL_M] = clk;



	/* PLLM_OUT1 */

drivers/clk/tegra/clk-tegra124.c

+3 −4
Original line number Diff line number Diff line
@@ -1089,8 +1089,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base, 


	/* PLLM */

	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,

			     CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,

			     &pll_m_params, NULL);

			     CLK_SET_RATE_GATE, &pll_m_params, NULL);

	clk_register_clkdev(clk, "pll_m", NULL);

	clks[TEGRA124_CLK_PLL_M] = clk;
@@ -1099,7 +1098,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base, 
				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,

				8, 8, 1, NULL);

	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",

				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |

				clk_base + PLLM_OUT, 1, 0,

				CLK_SET_RATE_PARENT, 0, NULL);

	clk_register_clkdev(clk, "pll_m_out1", NULL);

	clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
@@ -1272,7 +1271,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { 
	{ TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },

	{ TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },

	{ TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },

	{ TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },

	{ TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },

	{ TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },

	{ TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },

	{ TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },

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