Commit 2dca74a4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v5.8' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:
 "qcom:
   - new controller driver for IPCC
   - reorg the of_device data
   - add support for ipq6018 platform

  spreadtrum:
   - new sprd controller driver

  imx:
   - implement suspend/resume PM support

  misc:
   - make pcc driver struct static
   - fix return value in imx_mu_scu
   - disable clock before bailout in imx probe
   - remove duplicate error mssg in zynqmp probe
   - fix header size in imx.scu
   - check for null instead of is-err in zynqmp"

* tag 'mailbox-v5.8' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: qcom: Add ipq6018 apcs compatible
  mailbox: qcom: Add clock driver name in apcs mailbox driver data
  dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block
  mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flag
  mailbox: imx: Add runtime PM callback to handle MU clocks
  mailbox: imx: Add context save/restore for suspend/resume
  MAINTAINERS: Add entry for Qualcomm IPCC driver
  mailbox: Add support for Qualcomm IPCC
  dt-bindings: mailbox: Add devicetree binding for Qcom IPCC
  mailbox: zynqmp-ipi: Fix NULL vs IS_ERR() check in zynqmp_ipi_mbox_probe()
  mailbox: imx-mailbox: fix scu msg header size check
  mailbox: sprd: Add Spreadtrum mailbox driver
  dt-bindings: mailbox: Add the Spreadtrum mailbox documentation
  mailbox: ZynqMP IPI: Delete an error message in zynqmp_ipi_probe()
  mailbox: imx: Disable the clock on devm_mbox_controller_register() failure
  mailbox: imx: Fix return in imx_mu_scu_xlate()
  mailbox: imx: Support runtime PM
  mailbox: pcc: make pcc_mbox_driver static
parents e0154bd4 e9f901dc

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt

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Binding for the Qualcomm APCS global block

==========================================



This binding describes the APCS "global" block found in various Qualcomm

platforms.



- compatible:

	Usage: required

	Value type: <string>

	Definition: must be one of:

		    "qcom,msm8916-apcs-kpss-global",

		    "qcom,msm8996-apcs-hmss-global"

		    "qcom,msm8998-apcs-hmss-global"

		    "qcom,qcs404-apcs-apps-global"

		    "qcom,sc7180-apss-shared"

		    "qcom,sdm845-apss-shared"

		    "qcom,sm8150-apss-shared"

		    "qcom,ipq8074-apcs-apps-global"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: must specify the base address and size of the global block



- clocks:

	Usage: required if #clock-names property is present

	Value type: <phandle array>

	Definition: phandles to the two parent clocks of the clock driver.



- #mbox-cells:

	Usage: required

	Value type: <u32>

	Definition: as described in mailbox.txt, must be 1



- #clock-cells:

	Usage: optional

	Value type: <u32>

	Definition: as described in clock.txt, must be 0



- clock-names:

	Usage: required if the platform data based clock driver needs to

	retrieve the parent clock names from device tree.

	This will requires two mandatory clocks to be defined.

	Value type: <string-array>

	Definition: must be "pll" and "aux"



= EXAMPLE

The following example describes the APCS HMSS found in MSM8996 and part of the

GLINK RPM referencing the "rpm_hlos" doorbell therein.



	apcs_glb: mailbox@9820000 {

		compatible = "qcom,msm8996-apcs-hmss-global";

		reg = <0x9820000 0x1000>;



		#mbox-cells = <1>;

	};



	rpm-glink {

		compatible = "qcom,glink-rpm";



		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;



		qcom,rpm-msg-ram = <&rpm_msg_ram>;



		mboxes = <&apcs_glb 0>;

		mbox-names = "rpm_hlos";

	};



Below is another example of the APCS binding on MSM8916 platforms:



	apcs: mailbox@b011000 {

		compatible = "qcom,msm8916-apcs-kpss-global";

		reg = <0xb011000 0x1000>;

		#mbox-cells = <1>;

		clocks = <&a53pll>;

		#clock-cells = <0>;

	};



Below is another example of the APCS binding on QCS404 platforms:



	apcs_glb: mailbox@b011000 {

		compatible = "qcom,qcs404-apcs-apps-global", "syscon";

		reg = <0x0b011000 0x1000>;

		#mbox-cells = <1>;

		clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;

		clock-names = "pll", "aux";

		#clock-cells = <0>;

	};

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Qualcomm APCS global block bindings



description:

  This binding describes the APCS "global" block found in various Qualcomm

  platforms.



maintainers:

  - Sivaprakash Murugesan <sivaprak@codeaurora.org>



properties:

  compatible:

    enum:

      - qcom,ipq8074-apcs-apps-global

      - qcom,msm8916-apcs-kpss-global

      - qcom,msm8996-apcs-hmss-global

      - qcom,msm8998-apcs-hmss-global

      - qcom,qcs404-apcs-apps-global

      - qcom,sc7180-apss-shared

      - qcom,sdm845-apss-shared

      - qcom,sm8150-apss-shared



  reg:

    maxItems: 1



  clocks:

    description: phandles to the parent clocks of the clock driver

    items:

      - description: primary pll parent of the clock driver

      - description: auxiliary parent



  '#mbox-cells':

    const: 1



  '#clock-cells':

    const: 0



  clock-names:

    items:

      - const: pll

      - const: aux



required:

  - compatible

  - reg

  - '#mbox-cells'



additionalProperties: false



examples:



  # Example apcs with msm8996

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    apcs_glb: mailbox@9820000 {

        compatible = "qcom,msm8996-apcs-hmss-global";

        reg = <0x9820000 0x1000>;



        #mbox-cells = <1>;

    };



    rpm-glink {

        compatible = "qcom,glink-rpm";

        interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

        qcom,rpm-msg-ram = <&rpm_msg_ram>;

        mboxes = <&apcs_glb 0>;

        mbox-names = "rpm_hlos";

    };



  # Example apcs with qcs404

  - |

    #define GCC_APSS_AHB_CLK_SRC  1

    #define GCC_GPLL0_AO_OUT_MAIN 123

    apcs: mailbox@b011000 {

        compatible = "qcom,qcs404-apcs-apps-global";

        reg = <0x0b011000 0x1000>;

        #mbox-cells = <1>;

        clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;

        clock-names = "pll", "aux";

        #clock-cells = <0>;

    };

Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description:

  The Inter-Processor Communication Controller (IPCC) is a centralized hardware

  to route interrupts across various subsystems. It involves a three-level

  addressing scheme called protocol, client and signal. For example, consider an

  entity on the Application Processor Subsystem (APSS) that wants to listen to

  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such

  a case, the client would be Modem (client-id is 2) and the signal would be

  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)

  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h

  for the list of such IDs.



properties:

  compatible:

    items:

      - enum:

        - qcom,sm8250-ipcc

      - const: qcom,ipcc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  interrupt-controller: true



  "#interrupt-cells":

    const: 3

    description:

      The first cell is the client-id, the second cell is the signal-id and the

      third cell is the interrupt type.



  "#mbox-cells":

    const: 2

    description:

      The first cell is the client-id, and the second cell is the signal-id.



required:

  - compatible

  - reg

  - interrupts

  - interrupt-controller

  - "#interrupt-cells"

  - "#mbox-cells"



additionalProperties: false



examples:

  - |

        #include <dt-bindings/interrupt-controller/arm-gic.h>

        #include <dt-bindings/mailbox/qcom-ipcc.h>



        mailbox@408000 {

                compatible = "qcom,sm8250-ipcc", "qcom,ipcc";

                reg = <0x408000 0x1000>;

                interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;

                interrupt-controller;

                #interrupt-cells = <3>;

                #mbox-cells = <2>;

        };



        smp2p-modem {

                compatible = "qcom,smp2p";

                interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS

                                IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>;

                mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;



                /* Other SMP2P fields */

        };

Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Spreadtrum mailbox controller bindings



maintainers:

  - Orson Zhai <orsonzhai@gmail.com>

  - Baolin Wang <baolin.wang7@gmail.com>

  - Chunyan Zhang <zhang.lyra@gmail.com>



properties:

  compatible:

    enum:

      - sprd,sc9860-mailbox



  reg:

    items:

      - description: inbox registers' base address

      - description: outbox registers' base address



  interrupts:

    items:

      - description: inbox interrupt

      - description: outbox interrupt



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: enable



  "#mbox-cells":

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - "#mbox-cells"

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mailbox: mailbox@400a0000 {

      compatible = "sprd,sc9860-mailbox";

      reg = <0 0x400a0000 0 0x8000>, <0 0x400a8000 0 0x8000>;

      #mbox-cells = <1>;

      clock-names = "enable";

      clocks = <&aon_gate 53>;

      interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

    };

...

MAINTAINERS

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@@ -14187,6 +14187,14 @@ L: linux-arm-msm@vger.kernel.org 
S:	Maintained

F:	drivers/iommu/qcom_iommu.c













QUALCOMM IPCC MAILBOX DRIVER













M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>













L:	linux-arm-msm@vger.kernel.org













S:	Supported













F:	Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml













F:	drivers/mailbox/qcom-ipcc.c













F:	include/dt-bindings/mailbox/qcom-ipcc.h



























QUALCOMM RMNET DRIVER















M:	Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>















M:	Sean Tranchetti <stranche@codeaurora.org>









































































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