drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swing (2d69c42e) · Commits · 戴 / test

This sequence was recently added to fix internal HW sequences to reset TC ports. HSDES: 1507287614 HSDES: 14010071447 BSpec: 49292 Reviewed-by:

Lucas De Marchi <lucas.demarchi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:

drivers/gpu/drm/i915/display/intel_ddi.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -2838,6 +2838,8 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
		for (ln = 0; ln < 2; ln++) {
		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));

		I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);

		/* All the registers are RMW */
		val = I915_READ(DKL_TX_DPCNTL0(tc_port));
		val &= ~dpcnt_mask;

+6 −0

Original line number	Diff line number	Diff line
		@@ -10260,6 +10260,12 @@ enum skl_power_gate {
		_DKL_PHY2_BASE) + \
		_DKL_TX_FW_CALIB)

		#define _DKL_TX_PMD_LANE_SUS 0xD00
		#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
		_DKL_PHY1_BASE, \
		_DKL_PHY2_BASE) + \
		_DKL_TX_PMD_LANE_SUS)

		#define _DKL_TX_DW17 0xDC4
		#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
		_DKL_PHY1_BASE, \