Commit 2d591ab1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2015-11-19' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

i915 fixes for 4.4, including the revert for the backlight regression
Olof reported. Otherwise fixes all around.

* tag 'drm-intel-fixes-2015-11-19' of git://anongit.freedesktop.org/drm-intel:
  Revert "drm/i915: skip modeset if compatible for everyone."
  drm/i915: Consider SPLL as another shared pll, v2.
  drm/i915: Fix gpu frequency change tracing
  drm/i915: Don't clobber the addfb2 ioctl params
  drm/i915: Clear intel_crtc->atomic before updating it.
  drm/i915: get runtime PM reference around GEM set_caching IOCTL
  drm/i915: Fix GT frequency rounding
  drm/i915: quirk backlight present on Macbook 4, 1
  drm/i915: Fix crtc_y assignment in intel_find_initial_plane_obj()
parents db395637 73831236

drivers/gpu/drm/i915/i915_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -351,6 +351,8 @@ enum intel_dpll_id { 
	/* hsw/bdw */

	DPLL_ID_WRPLL1 = 0,

	DPLL_ID_WRPLL2 = 1,

	DPLL_ID_SPLL = 2,



	/* skl */

	DPLL_ID_SKL_DPLL1 = 0,

	DPLL_ID_SKL_DPLL2 = 1,
@@ -367,6 +369,7 @@ struct intel_dpll_hw_state { 


	/* hsw, bdw */

	uint32_t wrpll;

	uint32_t spll;



	/* skl */

	/*
@@ -2648,6 +2651,7 @@ struct i915_params { 
	int enable_cmd_parser;

	/* leave bools at the end to not create holes */

	bool enable_hangcheck;

	bool fastboot;

	bool prefault_disable;

	bool load_detect_test;

	bool reset;

drivers/gpu/drm/i915/i915_gem.c

+7 −1
Original line number Diff line number Diff line
@@ -3809,6 +3809,7 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,

			       struct drm_file *file)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_gem_caching *args = data;

	struct drm_i915_gem_object *obj;

	enum i915_cache_level level;
@@ -3837,9 +3838,11 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 
		return -EINVAL;

	}



	intel_runtime_pm_get(dev_priv);



	ret = i915_mutex_lock_interruptible(dev);

	if (ret)

		return ret;

		goto rpm_put;



	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));

	if (&obj->base == NULL) {
@@ -3852,6 +3855,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 
	drm_gem_object_unreference(&obj->base);

unlock:

	mutex_unlock(&dev->struct_mutex);

rpm_put:

	intel_runtime_pm_put(dev_priv);



	return ret;

}

drivers/gpu/drm/i915/i915_params.c

+5 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ struct i915_params i915 __read_mostly = { 
	.preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),

	.disable_power_well = -1,

	.enable_ips = 1,

	.fastboot = 0,

	.prefault_disable = 0,

	.load_detect_test = 0,

	.reset = true,
@@ -133,6 +134,10 @@ MODULE_PARM_DESC(disable_power_well, 
module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);

MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");



module_param_named(fastboot, i915.fastboot, bool, 0600);

MODULE_PARM_DESC(fastboot,

	"Try to skip unnecessary mode sets at boot time (default: false)");



module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600);

MODULE_PARM_DESC(prefault_disable,

	"Disable page prefaulting for pread/pwrite/reloc (default:false). "

drivers/gpu/drm/i915/intel_crt.c

+4 −27
Original line number Diff line number Diff line
@@ -138,18 +138,6 @@ static void hsw_crt_get_config(struct intel_encoder *encoder, 
	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);

}



static void hsw_crt_pre_enable(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");

	I915_WRITE(SPLL_CTL,

		   SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC);

	POSTING_READ(SPLL_CTL);

	udelay(20);

}



/* Note: The caller is required to filter out dpms modes not supported by the

 * platform. */

static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -216,19 +204,6 @@ static void pch_post_disable_crt(struct intel_encoder *encoder) 
	intel_disable_crt(encoder);

}



static void hsw_crt_post_disable(struct intel_encoder *encoder)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t val;



	DRM_DEBUG_KMS("Disabling SPLL\n");

	val = I915_READ(SPLL_CTL);

	WARN_ON(!(val & SPLL_PLL_ENABLE));

	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);

	POSTING_READ(SPLL_CTL);

}



static void intel_enable_crt(struct intel_encoder *encoder)

{

	struct intel_crt *crt = intel_encoder_to_crt(encoder);
@@ -280,6 +255,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder, 
	if (HAS_DDI(dev)) {

		pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;

		pipe_config->port_clock = 135000 * 2;



		pipe_config->dpll_hw_state.wrpll = 0;

		pipe_config->dpll_hw_state.spll =

			SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;

	}



	return true;
@@ -860,8 +839,6 @@ void intel_crt_init(struct drm_device *dev) 
	if (HAS_DDI(dev)) {

		crt->base.get_config = hsw_crt_get_config;

		crt->base.get_hw_state = intel_ddi_get_hw_state;

		crt->base.pre_enable = hsw_crt_pre_enable;

		crt->base.post_disable = hsw_crt_post_disable;

	} else {

		crt->base.get_config = intel_crt_get_config;

		crt->base.get_hw_state = intel_crt_get_hw_state;

drivers/gpu/drm/i915/intel_ddi.c

+65 −10
Original line number Diff line number Diff line
@@ -1286,6 +1286,18 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 
		}



		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);

	} else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {

		struct drm_atomic_state *state = crtc_state->base.state;

		struct intel_shared_dpll_config *spll =

			&intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];



		if (spll->crtc_mask &&

		    WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))

			return false;



		crtc_state->shared_dpll = DPLL_ID_SPLL;

		spll->hw_state.spll = crtc_state->dpll_hw_state.spll;

		spll->crtc_mask |= 1 << intel_crtc->pipe;

	}



	return true;
@@ -2437,7 +2449,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) 
	}

}



static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,

static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,

			       struct intel_shared_dpll *pll)

{

	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
@@ -2445,7 +2457,15 @@ static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 
	udelay(20);

}



static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,

static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,

				struct intel_shared_dpll *pll)

{

	I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);

	POSTING_READ(SPLL_CTL);

	udelay(20);

}



static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,

				  struct intel_shared_dpll *pll)

{

	uint32_t val;
@@ -2455,7 +2475,17 @@ static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 
	POSTING_READ(WRPLL_CTL(pll->id));

}



static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,

static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,

				 struct intel_shared_dpll *pll)

{

	uint32_t val;



	val = I915_READ(SPLL_CTL);

	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);

	POSTING_READ(SPLL_CTL);

}



static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,

				       struct intel_shared_dpll *pll,

				       struct intel_dpll_hw_state *hw_state)

{
@@ -2470,25 +2500,50 @@ static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 
	return val & WRPLL_PLL_ENABLE;

}



static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,

				      struct intel_shared_dpll *pll,

				      struct intel_dpll_hw_state *hw_state)

{

	uint32_t val;



	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))

		return false;



	val = I915_READ(SPLL_CTL);

	hw_state->spll = val;



	return val & SPLL_PLL_ENABLE;

}





static const char * const hsw_ddi_pll_names[] = {

	"WRPLL 1",

	"WRPLL 2",

	"SPLL"

};



static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)

{

	int i;



	dev_priv->num_shared_dpll = 2;

	dev_priv->num_shared_dpll = 3;



	for (i = 0; i < dev_priv->num_shared_dpll; i++) {

	for (i = 0; i < 2; i++) {

		dev_priv->shared_dplls[i].id = i;

		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];

		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;

		dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;

		dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;

		dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;

		dev_priv->shared_dplls[i].get_hw_state =

			hsw_ddi_pll_get_hw_state;

			hsw_ddi_wrpll_get_hw_state;

	}



	/* SPLL is special, but needs to be initialized anyway.. */

	dev_priv->shared_dplls[i].id = i;

	dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];

	dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;

	dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;

	dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;



}



static const char * const skl_ddi_pll_names[] = {

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