Commit 2d58b733 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: KVM: force cache clean on page fault when caches are off 



In order for the guest with caches off to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as
guest accesses are completely bypassing the cache until it
decides to enable it).

For this purpose, hook into the coherent_icache_guest_page
function and flush the region if the guest SCTLR_EL1
register doesn't show the MMU  and caches as being enabled.
The function also get renamed to coherent_cache_guest_page.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent 1b385cbd

arch/arm/include/asm/kvm_mmu.h

+2 −2
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd) 


struct kvm;



static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,

static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,

					     unsigned long size)

{

	/*

arch/arm/kvm/mmu.c

+2 −2
Original line number Diff line number Diff line
@@ -715,7 +715,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
			kvm_set_s2pmd_writable(&new_pmd);

			kvm_set_pfn_dirty(pfn);

		}

		coherent_icache_guest_page(kvm, hva & PMD_MASK, PMD_SIZE);

		coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE);

		ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);

	} else {

		pte_t new_pte = pfn_pte(pfn, PAGE_S2);
@@ -723,7 +723,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
			kvm_set_s2pte_writable(&new_pte);

			kvm_set_pfn_dirty(pfn);

		}

		coherent_icache_guest_page(kvm, hva, PAGE_SIZE);

		coherent_cache_guest_page(vcpu, hva, PAGE_SIZE);

		ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, false);

	}

arch/arm64/include/asm/kvm_mmu.h

+12 −4
Original line number Diff line number Diff line
@@ -106,7 +106,6 @@ static inline bool kvm_is_write_fault(unsigned long esr) 
	return true;

}



static inline void kvm_clean_dcache_area(void *addr, size_t size) {}

static inline void kvm_clean_pgd(pgd_t *pgd) {}

static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}

static inline void kvm_clean_pte(pte_t *pte) {}
@@ -124,9 +123,19 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd) 


struct kvm;



static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,

#define kvm_flush_dcache_to_poc(a,l)	__flush_dcache_area((a), (l))



static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)

{

	return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;

}



static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,

					     unsigned long size)

{

	if (!vcpu_has_cache_enabled(vcpu))

		kvm_flush_dcache_to_poc((void *)hva, size);



	if (!icache_is_aliasing()) {		/* PIPT */

		flush_icache_range(hva, hva + size);

	} else if (!icache_is_aivivt()) {	/* non ASID-tagged VIVT */
@@ -135,7 +144,6 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva, 
	}

}



#define kvm_flush_dcache_to_poc(a,l)	__flush_dcache_area((a), (l))

#define kvm_virt_to_phys(x)		__virt_to_phys((unsigned long)(x))



#endif /* __ASSEMBLY__ */

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