Commit 2d3d54bf authored by Christophe Kerello's avatar Christophe Kerello Committed by Miquel Raynal
Browse files

mtd: rawnand: stm32_fmc2: remove useless inline comments 



Remove inline comments that are useless since function label are
self explanatory.

Signed-off-by: default avatarChristophe Kerello <christophe.kerello@st.com>
Reviewed-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1588756279-17289-3-git-send-email-christophe.kerello@st.com
parent 71d1f1d5

drivers/mtd/nand/raw/stm32_fmc2_nand.c

+0 −40
Original line number Diff line number Diff line
@@ -281,7 +281,6 @@ static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base) 
	return container_of(base, struct stm32_fmc2_nfc, base);

}



/* Timings configuration */

static void stm32_fmc2_timings_init(struct nand_chip *chip)

{

	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
@@ -313,7 +312,6 @@ static void stm32_fmc2_timings_init(struct nand_chip *chip) 
	writel_relaxed(patt, fmc2->io_base + FMC2_PATT);

}



/* Controller configuration */

static void stm32_fmc2_setup(struct nand_chip *chip)

{

	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
@@ -341,7 +339,6 @@ static void stm32_fmc2_setup(struct nand_chip *chip) 
	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);

}



/* Select target */

static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr)

{

	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
@@ -353,11 +350,7 @@ static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr) 
		return 0;



	fmc2->cs_sel = nand->cs_used[chipnr];



	/* FMC2 setup routine */

	stm32_fmc2_setup(chip);



	/* Apply timings */

	stm32_fmc2_timings_init(chip);



	if (fmc2->dma_tx_ch && fmc2->dma_rx_ch) {
@@ -407,7 +400,6 @@ static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr) 
	return 0;

}



/* Set bus width to 16-bit or 8-bit */

static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)

{

	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
@@ -418,7 +410,6 @@ static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set) 
	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);

}



/* Enable/disable ECC */

static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)

{

	u32 pcr = readl(fmc2->io_base + FMC2_PCR);
@@ -429,7 +420,6 @@ static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable) 
	writel(pcr, fmc2->io_base + FMC2_PCR);

}



/* Enable irq sources in case of the sequencer is used */

static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)

{

	u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
@@ -441,7 +431,6 @@ static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2) 
	writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);

}



/* Disable irq sources in case of the sequencer is used */

static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2)

{

	u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
@@ -453,13 +442,11 @@ static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2) 
	fmc2->irq_state = FMC2_IRQ_UNKNOWN;

}



/* Clear irq sources in case of the sequencer is used */

static inline void stm32_fmc2_clear_seq_irq(struct stm32_fmc2_nfc *fmc2)

{

	writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, fmc2->io_base + FMC2_CSQICR);

}



/* Enable irq sources in case of bch is used */

static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2,

					     int mode)

{
@@ -475,7 +462,6 @@ static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2, 
	writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);

}



/* Disable irq sources in case of bch is used */

static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2)

{

	u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
@@ -488,7 +474,6 @@ static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2) 
	fmc2->irq_state = FMC2_IRQ_UNKNOWN;

}



/* Clear irq sources in case of bch is used */

static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)

{

	writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
@@ -549,10 +534,7 @@ static int stm32_fmc2_ham_calculate(struct nand_chip *chip, const u8 *data, 
	}



	heccr = readl_relaxed(fmc2->io_base + FMC2_HECCR);



	stm32_fmc2_ham_set_ecc(heccr, ecc);



	/* Disable ECC */

	stm32_fmc2_set_ecc(fmc2, false);



	return 0;
@@ -654,13 +636,11 @@ static int stm32_fmc2_bch_calculate(struct nand_chip *chip, const u8 *data, 
		ecc[12] = bchpbr;

	}



	/* Disable ECC */

	stm32_fmc2_set_ecc(fmc2, false);



	return 0;

}



/* BCH algorithm correction */

static int stm32_fmc2_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)

{

	u32 bchdsr0 = ecc_sta[0];
@@ -720,7 +700,6 @@ static int stm32_fmc2_bch_correct(struct nand_chip *chip, u8 *dat, 
	ecc_sta[3] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR3);

	ecc_sta[4] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR4);



	/* Disable ECC */

	stm32_fmc2_set_ecc(fmc2, false);



	return stm32_fmc2_bch_decode(chip->ecc.size, dat, ecc_sta);
@@ -1054,7 +1033,6 @@ static int stm32_fmc2_sequencer_write_page(struct nand_chip *chip, 
{

	int ret;



	/* Select the target */

	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);

	if (ret)

		return ret;
@@ -1069,7 +1047,6 @@ static int stm32_fmc2_sequencer_write_page_raw(struct nand_chip *chip, 
{

	int ret;



	/* Select the target */

	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);

	if (ret)

		return ret;
@@ -1153,7 +1130,6 @@ static int stm32_fmc2_sequencer_read_page(struct nand_chip *chip, u8 *buf, 
	u16 sta_map;

	int ret;



	/* Select the target */

	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);

	if (ret)

		return ret;
@@ -1199,7 +1175,6 @@ static int stm32_fmc2_sequencer_read_page_raw(struct nand_chip *chip, u8 *buf, 
	struct mtd_info *mtd = nand_to_mtd(chip);

	int ret;



	/* Select the target */

	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);

	if (ret)

		return ret;
@@ -1409,7 +1384,6 @@ static int stm32_fmc2_exec_op(struct nand_chip *chip, 
	return ret;

}



/* Controller initialization */

static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)

{

	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
@@ -1452,7 +1426,6 @@ static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2) 
	writel_relaxed(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);

}



/* Controller timings */

static void stm32_fmc2_calc_timings(struct nand_chip *chip,

				    const struct nand_sdr_timings *sdrt)

{
@@ -1596,14 +1569,11 @@ static int stm32_fmc2_setup_interface(struct nand_chip *chip, int chipnr, 
		return 0;



	stm32_fmc2_calc_timings(chip, sdrt);



	/* Apply timings */

	stm32_fmc2_timings_init(chip);



	return 0;

}



/* DMA configuration */

static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)

{

	int ret = 0;
@@ -1667,7 +1637,6 @@ err_dma: 
	return ret;

}



/* NAND callbacks setup */

static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)

{

	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
@@ -1708,7 +1677,6 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip) 
		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;

}



/* FMC2 layout */

static int stm32_fmc2_nand_ooblayout_ecc(struct mtd_info *mtd, int section,

					 struct mtd_oob_region *oobregion)

{
@@ -1744,7 +1712,6 @@ static const struct mtd_ooblayout_ops stm32_fmc2_nand_ooblayout_ops = { 
	.free = stm32_fmc2_nand_ooblayout_free,

};



/* FMC2 caps */

static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)

{

	/* Hamming */
@@ -1763,7 +1730,6 @@ NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes, 
		     FMC2_ECC_STEP_SIZE,

		     FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);



/* FMC2 controller ops */

static int stm32_fmc2_attach_chip(struct nand_chip *chip)

{

	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
@@ -1797,13 +1763,10 @@ static int stm32_fmc2_attach_chip(struct nand_chip *chip) 
	if (chip->bbt_options & NAND_BBT_USE_FLASH)

		chip->bbt_options |= NAND_BBT_NO_OOB;



	/* NAND callbacks setup */

	stm32_fmc2_nand_callbacks_setup(chip);



	/* Define ECC layout */

	mtd_set_ooblayout(mtd, &stm32_fmc2_nand_ooblayout_ops);



	/* Configure bus width to 16-bit */

	if (chip->options & NAND_BUSWIDTH_16)

		stm32_fmc2_set_buswidth_16(fmc2, true);
@@ -1816,7 +1779,6 @@ static const struct nand_controller_ops stm32_fmc2_nand_controller_ops = { 
	.setup_data_interface = stm32_fmc2_setup_interface,

};



/* FMC2 probe */

static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,

				  struct device_node *dn)

{
@@ -1976,12 +1938,10 @@ static int stm32_fmc2_probe(struct platform_device *pdev) 
		reset_control_deassert(rstc);

	}



	/* DMA setup */

	ret = stm32_fmc2_dma_setup(fmc2);

	if (ret)

		goto err_release_dma;



	/* FMC2 init routine */

	stm32_fmc2_init(fmc2);



	nand = &fmc2->nand;

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