Commit 2d1b69ed authored by Tariq Toukan's avatar Tariq Toukan Committed by Saeed Mahameed
Browse files

net/mlx5: kTLS, Improve TLS params layout structures 



Add explicit WQE segment structures for the TLS static and progress
params.
According to the HW spec, TISN is not part of the progress params context,
take it out of it.
Rename the control segment tisn field as it could hold either a TIS or
a TIR number.

Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 188f0f98

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h

+1 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, void __iomem *uar_map, 


static inline bool mlx5e_transport_inline_tx_wqe(struct mlx5_wqe_ctrl_seg *cseg)

{

	return cseg && !!cseg->tisn;

	return cseg && !!cseg->tis_tir_num;

}



static inline u8

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 


#define MLX5E_KTLS_PROGRESS_WQE_SZ \

	(offsetof(struct mlx5e_tx_wqe, tls_progress_params_ctx) + \

	 MLX5_ST_SZ_BYTES(tls_progress_params))

	 sizeof(struct mlx5_wqe_tls_progress_params_seg))

#define MLX5E_KTLS_PROGRESS_WQEBBS \

	(DIV_ROUND_UP(MLX5E_KTLS_PROGRESS_WQE_SZ, MLX5_SEND_WQE_BB))

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c

+9 −5
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ build_static_params(struct mlx5e_umr_wqe *wqe, u16 pc, u32 sqn, 
	cseg->qpn_ds           = cpu_to_be32((sqn << MLX5_WQE_CTRL_QPN_SHIFT) |

					     STATIC_PARAMS_DS_CNT);

	cseg->fm_ce_se         = fence ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;

	cseg->tisn             = cpu_to_be32(priv_tx->tisn << 8);

	cseg->tis_tir_num      = cpu_to_be32(priv_tx->tisn << 8);



	ucseg->flags = MLX5_UMR_INLINE;

	ucseg->bsf_octowords = cpu_to_be16(MLX5_ST_SZ_BYTES(tls_static_params) / 16);
@@ -75,10 +75,14 @@ build_static_params(struct mlx5e_umr_wqe *wqe, u16 pc, u32 sqn, 
static void

fill_progress_params_ctx(void *ctx, struct mlx5e_ktls_offload_context_tx *priv_tx)

{

	MLX5_SET(tls_progress_params, ctx, tisn, priv_tx->tisn);

	MLX5_SET(tls_progress_params, ctx, record_tracker_state,

	struct mlx5_wqe_tls_progress_params_seg *params;



	params = ctx;



	params->tis_tir_num = cpu_to_be32(priv_tx->tisn);

	MLX5_SET(tls_progress_params, params->ctx, record_tracker_state,

		 MLX5E_TLS_PROGRESS_PARAMS_RECORD_TRACKER_STATE_START);

	MLX5_SET(tls_progress_params, ctx, auth_state,

	MLX5_SET(tls_progress_params, params->ctx, auth_state,

		 MLX5E_TLS_PROGRESS_PARAMS_AUTH_STATE_NO_OFFLOAD);

}
@@ -284,7 +288,7 @@ tx_post_resync_dump(struct mlx5e_txqsq *sq, skb_frag_t *frag, u32 tisn, bool fir 


	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8)  | MLX5_OPCODE_DUMP);

	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);

	cseg->tisn             = cpu_to_be32(tisn << 8);

	cseg->tis_tir_num      = cpu_to_be32(tisn << 8);

	cseg->fm_ce_se         = first ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;



	fsz = skb_frag_size(frag);

drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c

+1 −1
Original line number Diff line number Diff line
@@ -305,7 +305,7 @@ err_out: 
void mlx5e_tls_handle_tx_wqe(struct mlx5e_txqsq *sq, struct mlx5_wqe_ctrl_seg *cseg,

			     struct mlx5e_accel_tx_tls_state *state)

{

	cseg->tisn = cpu_to_be32(state->tls_tisn << 8);

	cseg->tis_tir_num = cpu_to_be32(state->tls_tisn << 8);

}



static int tls_update_resync_sn(struct net_device *netdev,

include/linux/mlx5/device.h

+9 −0
Original line number Diff line number Diff line
@@ -458,6 +458,15 @@ enum { 
	MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,

};



struct mlx5_wqe_tls_static_params_seg {

	u8     ctx[MLX5_ST_SZ_BYTES(tls_static_params)];

};



struct mlx5_wqe_tls_progress_params_seg {

	__be32 tis_tir_num;

	u8     ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];

};



enum {

	MLX5_SET_PORT_RESET_QKEY	= 0,

	MLX5_SET_PORT_GUID0		= 16,

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