Commit 2d11fd3f authored by Trigger Huang's avatar Trigger Huang Committed by Alex Deucher
Browse files

drm/amdgpu: initialize PSP before IH under SR-IOV 



In order to support new PSP feature that PSP may provide interface
to program IH CNTL register, initialize PSP before IH under Vega10
SR-IOV VF

Signed-off-by: default avatarTrigger Huang <Trigger.Huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 78d48112

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −0
Original line number Diff line number Diff line
@@ -1580,6 +1580,7 @@ static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) 
		if (adev->ip_blocks[i].status.hw)

			continue;

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||

		    (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {

			r = adev->ip_blocks[i].version->funcs->hw_init(adev);

			if (r) {

drivers/gpu/drm/amd/amdgpu/soc15.c

+18 −6
Original line number Diff line number Diff line
@@ -608,6 +608,17 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_VEGA20:

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);



		/* For Vega10 SR-IOV, PSP need to be initialized before IH */

		if (amdgpu_sriov_vf(adev)) {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {

				if (adev->asic_type == CHIP_VEGA20)

					amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

				else

					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);

			}

			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

		} else {

			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {

				if (adev->asic_type == CHIP_VEGA20)
@@ -615,6 +626,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) 
				else

					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);

			}

		}

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		if (!amdgpu_sriov_vf(adev)) {

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