ARM: dts: imx6sll-evk: enable usdhc3 slot (2d0b768b) · Commits · 戴 / test

arch/arm/boot/dts/imx6sll-evk.dts

+65 −0

Original line number	Diff line number	Diff line
		@@ -88,6 +88,17 @@
		gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		};

		reg_sd3_vmmc: regulator-sd3-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_sd3_vmmc>;
		regulator-name = "SD3_WIFI";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		};
		};

		&cpu0 {
		@@ -239,7 +250,25 @@
		status = "okay";
		};

		&usdhc3 {
		pinctrl-names = "default", "state_100mhz", "state_200mhz";
		pinctrl-0 = <&pinctrl_usdhc3>;
		pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
		pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
		cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
		keep-power-in-suspend;
		enable-sdio-wakeup;
		vmmc-supply = <&reg_sd3_vmmc>;
		status = "okay";
		};

		&iomuxc {
		pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
		fsl,pins = <
		MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
		>;
		};

		pinctrl_usb_otg1_vbus: vbus1grp {
		fsl,pins = <
		MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
		@@ -310,6 +339,42 @@
		>;
		};

		pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
		MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061
		MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061
		MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061
		MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061
		MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061
		MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061
		MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
		>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
		MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1
		MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1
		MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1
		MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1
		MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1
		MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1
		MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
		>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
		MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9
		MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
		MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9
		MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9
		MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9
		MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9
		MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
		>;
		};

		pinctrl_i2c1: i2c1grp {
		fsl,pins = <
		MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1

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