Commit 2cffa11e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-core-2020-12-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "Generic interrupt and irqchips subsystem updates. Unusually, there is
  not a single completely new irq chip driver, just new DT bindings and
  extensions of existing drivers to accomodate new variants!

  Core:

   - Consolidation and robustness changes for irq time accounting

   - Cleanup and consolidation of irq stats

   - Remove the fasteoi IPI flow which has been proved useless

   - Provide an interface for converting legacy interrupt mechanism into
     irqdomains

  Drivers:

   - Preliminary support for managed interrupts on platform devices

   - Correctly identify allocation of MSIs proxyied by another device

   - Generalise the Ocelot support to new SoCs

   - Improve GICv4.1 vcpu entry, matching the corresponding KVM
     optimisation

   - Work around spurious interrupts on Qualcomm PDC

   - Random fixes and cleanups"

* tag 'irq-core-2020-12-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (54 commits)
  irqchip/qcom-pdc: Fix phantom irq when changing between rising/falling
  driver core: platform: Add devm_platform_get_irqs_affinity()
  ACPI: Drop acpi_dev_irqresource_disabled()
  resource: Add irqresource_disabled()
  genirq/affinity: Add irq_update_affinity_desc()
  irqchip/gic-v3-its: Flag device allocation as proxied if behind a PCI bridge
  irqchip/gic-v3-its: Tag ITS device as shared if allocating for a proxy device
  platform-msi: Track shared domain allocation
  irqchip/ti-sci-intr: Fix freeing of irqs
  irqchip/ti-sci-inta: Fix printing of inta id on probe success
  drivers/irqchip: Remove EZChip NPS interrupt controller
  Revert "genirq: Add fasteoi IPI flow"
  irqchip/hip04: Make IPIs use handle_percpu_devid_irq()
  irqchip/bcm2836: Make IPIs use handle_percpu_devid_irq()
  irqchip/armada-370-xp: Make IPIs use handle_percpu_devid_irq()
  irqchip/gic, gic-v3: Make SGIs use handle_percpu_devid_irq()
  irqchip/ocelot: Add support for Jaguar2 platforms
  irqchip/ocelot: Add support for Serval platforms
  irqchip/ocelot: Add support for Luton platforms
  irqchip/ocelot: prepare to support more SoC
  ...
parents 5b200f57 3c41e57a

Documentation/core-api/irq/irq-domain.rst

+6 −0
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ Legacy 
	irq_domain_add_simple()

	irq_domain_add_legacy()

	irq_domain_add_legacy_isa()

	irq_domain_create_legacy()



The Legacy mapping is a special case for drivers that already have a

range of irq_descs allocated for the hwirqs.  It is used when the
@@ -185,6 +186,11 @@ that the driver using the simple domain call irq_create_mapping() 
before any irq_find_mapping() since the latter will actually work

for the static IRQ assignment case.



irq_domain_add_legacy() and irq_domain_create_legacy() are functionally

equivalent, except for the first argument is different - the former

accepts an Open Firmware specific 'struct device_node', while the latter

accepts a more general abstraction 'struct fwnode_handle'.



Hierarchy IRQ domain

--------------------

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt

+6 −2
Original line number Diff line number Diff line 
* Freescale Layerscape external IRQs



Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting

Some Layerscape SOCs (LS1021A, LS1043A, LS1046A

LS1088A, LS208xA, LX216xA) support inverting

the polarity of certain external interrupt lines.



The device node must be a child of the node representing the
@@ -8,12 +9,15 @@ Supplemental Configuration Unit (SCFG). 


Required properties:

- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".

  "fsl,ls1043a-extirq": for LS1043A, LS1046A.

  "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.

- #interrupt-cells: Must be 2. The first element is the index of the

  external interrupt line. The second element is the trigger type.

- #address-cells: Must be 0.

- interrupt-controller: Identifies the node as an interrupt controller

- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in

  the SCFG.

  the SCFG or the External Interrupt Control Register (IRQCR) in

  the ISC.

- interrupt-map: Specifies the mapping from external interrupts to GIC

  interrupts.

- interrupt-map-mask: Must be <0xffffffff 0>.

Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt

deleted100644 → 0
+0 −21
Original line number Diff line number Diff line 
Microsemi Ocelot SoC ICPU Interrupt Controller



Required properties:



- compatible : should be "mscc,ocelot-icpu-intr"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.

- interrupts : Specifies the CPU interrupt the controller is connected to.



Example:



		intc: interrupt-controller@70000070 {

			compatible = "mscc,ocelot-icpu-intr";

			reg = <0x70000070 0x70>;

			#interrupt-cells = <1>;

			interrupt-controller;

			interrupt-parent = <&cpuintc>;

			interrupts = <2>;

		};

Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml

0 → 100644
+64 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Microsemi Ocelot SoC ICPU Interrupt Controller



maintainers:

  - Alexandre Belloni <alexandre.belloni@bootlin.com>



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



description: |

  the Microsemi Ocelot interrupt controller that is part of the

  ICPU. It is connected directly to the MIPS core interrupt

  controller.



properties:

  compatible:

    items:

      - enum:

          - mscc,jaguar2-icpu-intr

          - mscc,luton-icpu-intr

          - mscc,ocelot-icpu-intr

          - mscc,serval-icpu-intr





  '#interrupt-cells':

    const: 1



  '#address-cells':

    const: 0



  interrupt-controller: true



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - '#interrupt-cells'

  - '#address-cells'

  - interrupt-controller

  - reg



additionalProperties: false



examples:

  - |

    intc: interrupt-controller@70000070 {

        compatible = "mscc,ocelot-icpu-intr";

        reg = <0x70000070 0x70>;

        #interrupt-cells = <1>;

        #address-cells = <0>;

        interrupt-controller;

        interrupt-parent = <&cpuintc>;

        interrupts = <2>;

    };

...

arch/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -644,6 +644,12 @@ config HAVE_TIF_NOHZ 
config HAVE_VIRT_CPU_ACCOUNTING

	bool



config HAVE_VIRT_CPU_ACCOUNTING_IDLE

	bool

	help

	  Architecture has its own way to account idle CPU time and therefore

	  doesn't implement vtime_account_idle().



config ARCH_HAS_SCALED_CPUTIME

	bool
@@ -658,7 +664,6 @@ config HAVE_VIRT_CPU_ACCOUNTING_GEN 
	  some 32-bit arches may require multiple accesses, so proper

	  locking is needed to protect against concurrent accesses.





config HAVE_IRQ_TIME_ACCOUNTING

	bool

	help

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