Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus (2cc91884) · Commits · 戴 / test

Pull MIPS fixes from Ralf Baechle: "This is the first round of fixes and tying up loose ends for MIPS. - plenty of fixes for build errors in specific obscure configurations - remove redundant code on the Lantiq platform - removal of a useless SEAD I2C driver that was causing a build issue - fix an earlier TLB exeption handler fix to also work on Octeon. - fix ISA level dependencies in FPU emulator's instruction decoding. - don't hardcode kernel command line in Octeon software emulator. - fix an earlier fix for the Loondson 2 clock setting" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: SEAD3: Fix I2C device registration. MIPS: SEAD3: Nuke PIC32 I2C driver. MIPS: ftrace: Fix a microMIPS build problem MIPS: MSP71xx: Fix build error MIPS: Malta: Do not build the malta-amon.c file if CMP is not enabled MIPS: Prevent compiler warning from cop2_{save,restore} MIPS: Kconfig: Add missing MIPS_CPS dependencies to PM and cpuidle MIPS: idle: Remove leftover __pastwait symbol and its references MIPS: Sibyte: Include the swarm subdir to the sb1250 LittleSur builds MIPS: ptrace.h: Add a missing include MIPS: ath79: Fix compilation error when CONFIG_PCI is disabled MIPS: MSP71xx: Remove compilation error when CONFIG_MIPS_MT is present MIPS: Octeon: Remove special case for simulator command line. MIPS: tlbex: Properly fix HUGE TLB Refill exception handler MIPS: loongson2_cpufreq: Fix CPU clock rate setting mismerge pci: pci-lantiq: remove duplicate check on resource MIPS: Lasat: Add missing CONFIG_PROC_FS dependency to PICVUE_PROC MIPS: cp1emu: Fix ISA restrictions for cop1x_op instructions

arch/mips/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -2066,6 +2066,7 @@ config MIPS_CPS
		support is unavailable.

		config MIPS_CPS_PM
		depends on MIPS_CPS
		select MIPS_CPC
		bool

arch/mips/ath79/mach-db120.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -113,7 +113,7 @@ static void __init db120_pci_init(u8 *eeprom)
		ath79_register_pci();
		}
		#else
		static inline void db120_pci_init(void) {}
		static inline void db120_pci_init(u8 *eeprom) {}
		#endif /* CONFIG_PCI */

		static void __init db120_setup(void)

arch/mips/cavium-octeon/setup.c

+0 −9

Original line number	Diff line number	Diff line
		@@ -806,15 +806,6 @@ void __init prom_init(void)
		#endif
		}

		if (octeon_is_simulation()) {
		/*
		* The simulator uses a mtdram device pre filled with
		* the filesystem. Also specify the calibration delay
		* to avoid calculating it every time.
		*/
		strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
		}

		mips_hpt_frequency = octeon_get_clock_rate();

		octeon_init_cvmcount();

arch/mips/include/asm/cop2.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -37,15 +37,15 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);

		#define cop2_present 1
		#define cop2_lazy_restore 1
		#define cop2_save(r) do { (r); } while (0)
		#define cop2_restore(r) do { (r); } while (0)
		#define cop2_save(r) do { (void)(r); } while (0)
		#define cop2_restore(r) do { (void)(r); } while (0)

		#else

		#define cop2_present 0
		#define cop2_lazy_restore 0
		#define cop2_save(r) do { (r); } while (0)
		#define cop2_restore(r) do { (r); } while (0)
		#define cop2_save(r) do { (void)(r); } while (0)
		#define cop2_restore(r) do { (void)(r); } while (0)
		#endif

		enum cu2_ops {

arch/mips/include/asm/ftrace.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -24,7 +24,7 @@ do { \
		asm volatile ( \
		"1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
		" li %[tmp_err], 0\n" \
		"2:\n" \
		"2: .insn\n" \
		\
		".section .fixup, \"ax\"\n" \
		"3: li %[tmp_err], 1\n" \
		@@ -46,7 +46,7 @@ do { \
		asm volatile ( \
		"1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
		" li %[tmp_err], 0\n" \
		"2:\n" \
		"2: .insn\n" \
		\
		".section .fixup, \"ax\"\n" \
		"3: li %[tmp_err], 1\n" \

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