Commit 2c29eef9 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/vdso32: Don't read cache line size from the datapage on PPC32. 



On PPC32, the cache lines have a fixed size known at build time.

Don't read it from the datapage.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/dfa7b35e27e01964fcda84bf1ed8b2b31cf93826.1575273217.git.christophe.leroy@c-s.fr
parent ec0895f0

arch/powerpc/include/asm/vdso_datapage.h

+0 −4
Original line number Diff line number Diff line
@@ -108,10 +108,6 @@ struct vdso_data { 
	__u32 stamp_sec_fraction;	/* fractional seconds of stamp_xtime */

	__u32 hrtimer_res;		/* hrtimer resolution */

   	__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */

	__u32 dcache_block_size;	/* L1 d-cache block size     */

	__u32 icache_block_size;	/* L1 i-cache block size     */

	__u32 dcache_log_block_size;	/* L1 d-cache log block size */

	__u32 icache_log_block_size;	/* L1 i-cache log block size */

};



#endif /* CONFIG_PPC64 */

arch/powerpc/kernel/asm-offsets.c

+1 −1
Original line number Diff line number Diff line
@@ -389,11 +389,11 @@ int main(void) 
	OFFSET(STAMP_XTIME_NSEC, vdso_data, stamp_xtime_nsec);

	OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);

	OFFSET(CLOCK_HRTIMER_RES, vdso_data, hrtimer_res);

#ifdef CONFIG_PPC64

	OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);

	OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);

	OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);

	OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);

#ifdef CONFIG_PPC64

	OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);

	OFFSET(TVAL64_TV_SEC, __kernel_old_timeval, tv_sec);

	OFFSET(TVAL64_TV_USEC, __kernel_old_timeval, tv_usec);

arch/powerpc/kernel/vdso.c

+0 −5
Original line number Diff line number Diff line
@@ -728,11 +728,6 @@ static int __init vdso_init(void) 
	 */

	vdso64_pages = (&vdso64_end - &vdso64_start) >> PAGE_SHIFT;

	DBG("vdso64_kbase: %p, 0x%x pages\n", vdso64_kbase, vdso64_pages);

#else

	vdso_data->dcache_block_size = L1_CACHE_BYTES;

	vdso_data->dcache_log_block_size = L1_CACHE_SHIFT;

	vdso_data->icache_block_size = L1_CACHE_BYTES;

	vdso_data->icache_log_block_size = L1_CACHE_SHIFT;

#endif /* CONFIG_PPC64 */

arch/powerpc/kernel/vdso32/cacheflush.S

+23 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <asm/vdso.h>

#include <asm/vdso_datapage.h>

#include <asm/asm-offsets.h>

#include <asm/cache.h>



	.text
@@ -23,28 +24,44 @@ 
 */

V_FUNCTION_BEGIN(__kernel_sync_dicache)

  .cfi_startproc

#ifdef CONFIG_PPC64

	mflr	r12

  .cfi_register lr,r12

	get_datapage	r10, r0

	mtlr	r12

#endif



#ifdef CONFIG_PPC64

	lwz	r7,CFG_DCACHE_BLOCKSZ(r10)

	addi	r5,r7,-1

#else

	li	r5, L1_CACHE_BYTES - 1

#endif

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

#ifdef CONFIG_PPC64

	lwz	r9,CFG_DCACHE_LOGBLOCKSZ(r10)

	srw.	r8,r8,r9		/* compute line count */

#else

	srwi.	r8, r8, L1_CACHE_SHIFT

	mr	r7, r6

#endif

	crclr	cr0*4+so

	beqlr				/* nothing to do? */

	mtctr	r8

1:	dcbst	0,r6

#ifdef CONFIG_PPC64

	add	r6,r6,r7

#else

	addi	r6, r6, L1_CACHE_BYTES

#endif

	bdnz	1b

	sync



/* Now invalidate the instruction cache */



#ifdef CONFIG_PPC64

	lwz	r7,CFG_ICACHE_BLOCKSZ(r10)

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */
@@ -54,9 +71,15 @@ V_FUNCTION_BEGIN(__kernel_sync_dicache) 
	srw.	r8,r8,r9		/* compute line count */

	crclr	cr0*4+so

	beqlr				/* nothing to do? */

#endif

	mtctr	r8

#ifdef CONFIG_PPC64

2:	icbi	0,r6

	add	r6,r6,r7

#else

2:	icbi	0, r7

	addi	r7, r7, L1_CACHE_BYTES

#endif

	bdnz	2b

	isync

	li	r3,0

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