Commit 2c0408dd authored Dec 20, 2018 by Alexander Shiyan Committed by Philipp Zabel Jan 17, 2019

gpu: ipu-v3: Fix i.MX51 CSI control registers offset



The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.

Fixes: 2ffd48f2 ("gpu: ipu-v3: Add Camera Sensor Interface unit")

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

parent 4fb873c9

drivers/gpu/ipu-v3/ipu-common.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = {
		.cpmem_ofs = 0x1f000000,
		.srm_ofs = 0x1f040000,
		.tpm_ofs = 0x1f060000,
		.csi0_ofs = 0x1f030000,
		.csi1_ofs = 0x1f038000,
		.csi0_ofs = 0x1e030000,
		.csi1_ofs = 0x1e038000,
		.ic_ofs = 0x1e020000,
		.disp0_ofs = 0x1e040000,
		.disp1_ofs = 0x1e048000,

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