interconnect: qcom: Lay the groundwork for adding EPSS support (2bf706ea) · Commits · 戴 / test

drivers/interconnect/qcom/osm-l3.c

+26 −11

Original line number	Diff line number	Diff line
		@@ -21,13 +21,13 @@
		#define LUT_MAX_ENTRIES 40U
		#define LUT_SRC GENMASK(31, 30)
		#define LUT_L_VAL GENMASK(7, 0)
		#define LUT_ROW_SIZE 32
		#define CLK_HW_DIV 2

		/* Register offsets */
		/* OSM Register offsets */
		#define REG_ENABLE 0x0
		#define REG_FREQ_LUT 0x110
		#define REG_PERF_STATE 0x920
		#define OSM_LUT_ROW_SIZE 32
		#define OSM_REG_FREQ_LUT 0x110
		#define OSM_REG_PERF_STATE 0x920

		#define OSM_L3_MAX_LINKS 1

		@@ -37,6 +37,7 @@
		struct qcom_osm_l3_icc_provider {
		void __iomem *base;
		unsigned int max_state;
		unsigned int reg_perf_state;
		unsigned long lut_tables[LUT_MAX_ENTRIES];
		struct icc_provider provider;
		};
		@@ -60,6 +61,9 @@ struct qcom_icc_node {
		struct qcom_icc_desc {
		struct qcom_icc_node **nodes;
		size_t num_nodes;
		unsigned int lut_row_size;
		unsigned int reg_freq_lut;
		unsigned int reg_perf_state;
		};

		#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
		@@ -82,6 +86,9 @@ static struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
		static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
		.nodes = sdm845_osm_l3_nodes,
		.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
		.lut_row_size = OSM_LUT_ROW_SIZE,
		.reg_freq_lut = OSM_REG_FREQ_LUT,
		.reg_perf_state = OSM_REG_PERF_STATE,
		};

		DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
		@@ -95,6 +102,9 @@ static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
		static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
		.nodes = sc7180_osm_l3_nodes,
		.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
		.lut_row_size = OSM_LUT_ROW_SIZE,
		.reg_freq_lut = OSM_REG_FREQ_LUT,
		.reg_perf_state = OSM_REG_PERF_STATE,
		};

		DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
		@@ -108,6 +118,9 @@ static struct qcom_icc_node *sm8150_osm_l3_nodes[] = {
		static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
		.nodes = sm8150_osm_l3_nodes,
		.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
		.lut_row_size = OSM_LUT_ROW_SIZE,
		.reg_freq_lut = OSM_REG_FREQ_LUT,
		.reg_perf_state = OSM_REG_PERF_STATE,
		};

		static int qcom_icc_set(struct icc_node src, struct icc_node dst)
		@@ -138,7 +151,7 @@ static int qcom_icc_set(struct icc_node src, struct icc_node dst)
		break;
		}

		writel_relaxed(index, qp->base + REG_PERF_STATE);
		writel_relaxed(index, qp->base + qp->reg_perf_state);

		return 0;
		}
		@@ -193,9 +206,15 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
		return -ENODEV;
		}

		desc = device_get_match_data(&pdev->dev);
		if (!desc)
		return -EINVAL;

		qp->reg_perf_state = desc->reg_perf_state;

		for (i = 0; i < LUT_MAX_ENTRIES; i++) {
		info = readl_relaxed(qp->base + REG_FREQ_LUT +
		i * LUT_ROW_SIZE);
		info = readl_relaxed(qp->base + desc->reg_freq_lut +
		i * desc->lut_row_size);
		src = FIELD_GET(LUT_SRC, info);
		lval = FIELD_GET(LUT_L_VAL, info);
		if (src)
		@@ -214,10 +233,6 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
		}
		qp->max_state = i;

		desc = device_get_match_data(&pdev->dev);
		if (!desc)
		return -EINVAL;

		qnodes = desc->nodes;
		num_nodes = desc->num_nodes;

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