Commit 2bd7c3e1 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-hns3-add-some-optimizations-and-cleanups' 



Huazhong Tan says:

====================
net: hns3: add some optimizations and cleanups

This series adds some code optimizations and cleanups for
the HNS3 ethernet driver.

[patch 1/9] dumps some debug information when reset fail.

[patch 2/9] dumps some struct netdev_queue information when
TX timeout.

[patch 3/9] cleanups some magic numbers.

[patch 4/9] cleanups some coding style issue.

[patch 5/9] fixes a compiler warning.

[patch 6/9] optimizes some local variable initialization.

[patch 7/9] modifies some comments.

[patch 8/9] cleanups some print format warnings.

[patch 9/9] cleanups byte order issue.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 79697744 39edaf24

drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h

+2 −2
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ enum HCLGE_MBX_OPCODE { 
	HCLGE_MBX_GET_MEDIA_TYPE,       /* (VF -> PF) get media type */

	HCLGE_MBX_PUSH_PROMISC_INFO,	/* (PF -> VF) push vf promisc info */



	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf reset status */

	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */

	HCLGE_MBX_PUSH_LINK_STATUS,	/* (M7 -> PF) get port link status */

	HCLGE_MBX_NCSI_ERROR,		/* (M7 -> PF) receive a NCSI error */

};
@@ -72,7 +72,7 @@ enum hclge_mbx_vlan_cfg_subcode { 
};



#define HCLGE_MBX_MAX_MSG_SIZE	16

#define HCLGE_MBX_MAX_RESP_DATA_SIZE	8

#define HCLGE_MBX_MAX_RESP_DATA_SIZE	8U

#define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM	3

#define HCLGE_MBX_RING_NODE_VARIABLE_NUM	3

drivers/net/ethernet/hisilicon/hns3/hnae3.c

+1 −1
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ void hnae3_unregister_client(struct hnae3_client *client) 
		return;



	mutex_lock(&hnae3_common_lock);



	/* one system should only have one client for every type */

	list_for_each_entry(client_tmp, &hnae3_client_list, node) {

		if (client_tmp->type == client->type) {

			existed = true;

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+2 −2
Original line number Diff line number Diff line
@@ -130,7 +130,6 @@ enum hnae3_module_type { 
	HNAE3_MODULE_TYPE_CR		= 0x04,

	HNAE3_MODULE_TYPE_KR		= 0x05,

	HNAE3_MODULE_TYPE_TP		= 0x06,



};



enum hnae3_fec_mode {
@@ -576,7 +575,8 @@ struct hnae3_ae_algo { 
	const struct pci_device_id *pdev_id_table;

};



#define HNAE3_INT_NAME_LEN        (IFNAMSIZ + 16)

#define HNAE3_INT_NAME_EXT_LEN    32	 /* Max extra information length */

#define HNAE3_INT_NAME_LEN        (IFNAMSIZ + HNAE3_INT_NAME_EXT_LEN)

#define HNAE3_ITR_COUNTDOWN_START 100



struct hnae3_tc_info {

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+38 −31
Original line number Diff line number Diff line
@@ -57,68 +57,68 @@ static int hns3_dbg_queue_info(struct hnae3_handle *h, 
					   HNS3_RING_RX_RING_BASEADDR_H_REG);

		base_add_l = readl_relaxed(ring->tqp->io_base +

					   HNS3_RING_RX_RING_BASEADDR_L_REG);

		dev_info(&h->pdev->dev, "RX(%d) BASE ADD: 0x%08x%08x\n", i,

		dev_info(&h->pdev->dev, "RX(%u) BASE ADD: 0x%08x%08x\n", i,

			 base_add_h, base_add_l);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_RX_RING_BD_NUM_REG);

		dev_info(&h->pdev->dev, "RX(%d) RING BD NUM: %u\n", i, value);

		dev_info(&h->pdev->dev, "RX(%u) RING BD NUM: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_RX_RING_BD_LEN_REG);

		dev_info(&h->pdev->dev, "RX(%d) RING BD LEN: %u\n", i, value);

		dev_info(&h->pdev->dev, "RX(%u) RING BD LEN: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_RX_RING_TAIL_REG);

		dev_info(&h->pdev->dev, "RX(%d) RING TAIL: %u\n", i, value);

		dev_info(&h->pdev->dev, "RX(%u) RING TAIL: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_RX_RING_HEAD_REG);

		dev_info(&h->pdev->dev, "RX(%d) RING HEAD: %u\n", i, value);

		dev_info(&h->pdev->dev, "RX(%u) RING HEAD: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_RX_RING_FBDNUM_REG);

		dev_info(&h->pdev->dev, "RX(%d) RING FBDNUM: %u\n", i, value);

		dev_info(&h->pdev->dev, "RX(%u) RING FBDNUM: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_RX_RING_PKTNUM_RECORD_REG);

		dev_info(&h->pdev->dev, "RX(%d) RING PKTNUM: %u\n", i, value);

		dev_info(&h->pdev->dev, "RX(%u) RING PKTNUM: %u\n", i, value);



		ring = &priv->ring[i];

		base_add_h = readl_relaxed(ring->tqp->io_base +

					   HNS3_RING_TX_RING_BASEADDR_H_REG);

		base_add_l = readl_relaxed(ring->tqp->io_base +

					   HNS3_RING_TX_RING_BASEADDR_L_REG);

		dev_info(&h->pdev->dev, "TX(%d) BASE ADD: 0x%08x%08x\n", i,

		dev_info(&h->pdev->dev, "TX(%u) BASE ADD: 0x%08x%08x\n", i,

			 base_add_h, base_add_l);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_BD_NUM_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING BD NUM: %u\n", i, value);

		dev_info(&h->pdev->dev, "TX(%u) RING BD NUM: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_TC_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING TC: %u\n", i, value);

		dev_info(&h->pdev->dev, "TX(%u) RING TC: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_TAIL_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING TAIL: %u\n", i, value);

		dev_info(&h->pdev->dev, "TX(%u) RING TAIL: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_HEAD_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING HEAD: %u\n", i, value);

		dev_info(&h->pdev->dev, "TX(%u) RING HEAD: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_FBDNUM_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING FBDNUM: %u\n", i, value);

		dev_info(&h->pdev->dev, "TX(%u) RING FBDNUM: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_OFFSET_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING OFFSET: %u\n", i, value);

		dev_info(&h->pdev->dev, "TX(%u) RING OFFSET: %u\n", i, value);



		value = readl_relaxed(ring->tqp->io_base +

				      HNS3_RING_TX_RING_PKTNUM_RECORD_REG);

		dev_info(&h->pdev->dev, "TX(%d) RING PKTNUM: %u\n\n", i,

		dev_info(&h->pdev->dev, "TX(%u) RING PKTNUM: %u\n\n", i,

			 value);

	}
@@ -190,21 +190,24 @@ static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf) 
	addr = le64_to_cpu(tx_desc->addr);

	dev_info(dev, "TX Queue Num: %u, BD Index: %u\n", q_num, tx_index);

	dev_info(dev, "(TX)addr: %pad\n", &addr);

	dev_info(dev, "(TX)vlan_tag: %u\n", tx_desc->tx.vlan_tag);

	dev_info(dev, "(TX)send_size: %u\n", tx_desc->tx.send_size);

	dev_info(dev, "(TX)vlan_tag: %u\n", le16_to_cpu(tx_desc->tx.vlan_tag));

	dev_info(dev, "(TX)send_size: %u\n",

		 le16_to_cpu(tx_desc->tx.send_size));

	dev_info(dev, "(TX)vlan_tso: %u\n", tx_desc->tx.type_cs_vlan_tso);

	dev_info(dev, "(TX)l2_len: %u\n", tx_desc->tx.l2_len);

	dev_info(dev, "(TX)l3_len: %u\n", tx_desc->tx.l3_len);

	dev_info(dev, "(TX)l4_len: %u\n", tx_desc->tx.l4_len);

	dev_info(dev, "(TX)vlan_tag: %u\n", tx_desc->tx.outer_vlan_tag);

	dev_info(dev, "(TX)tv: %u\n", tx_desc->tx.tv);

	dev_info(dev, "(TX)vlan_tag: %u\n",

		 le16_to_cpu(tx_desc->tx.outer_vlan_tag));

	dev_info(dev, "(TX)tv: %u\n", le16_to_cpu(tx_desc->tx.tv));

	dev_info(dev, "(TX)vlan_msec: %u\n", tx_desc->tx.ol_type_vlan_msec);

	dev_info(dev, "(TX)ol2_len: %u\n", tx_desc->tx.ol2_len);

	dev_info(dev, "(TX)ol3_len: %u\n", tx_desc->tx.ol3_len);

	dev_info(dev, "(TX)ol4_len: %u\n", tx_desc->tx.ol4_len);

	dev_info(dev, "(TX)paylen: %u\n", tx_desc->tx.paylen);

	dev_info(dev, "(TX)vld_ra_ri: %u\n", tx_desc->tx.bdtp_fe_sc_vld_ra_ri);

	dev_info(dev, "(TX)mss: %u\n", tx_desc->tx.mss);

	dev_info(dev, "(TX)paylen: %u\n", le32_to_cpu(tx_desc->tx.paylen));

	dev_info(dev, "(TX)vld_ra_ri: %u\n",

		 le16_to_cpu(tx_desc->tx.bdtp_fe_sc_vld_ra_ri));

	dev_info(dev, "(TX)mss: %u\n", le16_to_cpu(tx_desc->tx.mss));



	ring  = &priv->ring[q_num + h->kinfo.num_tqps];

	value = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_TAIL_REG);
@@ -214,15 +217,19 @@ static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf) 
	addr = le64_to_cpu(rx_desc->addr);

	dev_info(dev, "RX Queue Num: %u, BD Index: %u\n", q_num, rx_index);

	dev_info(dev, "(RX)addr: %pad\n", &addr);

	dev_info(dev, "(RX)l234_info: %u\n", rx_desc->rx.l234_info);

	dev_info(dev, "(RX)pkt_len: %u\n", rx_desc->rx.pkt_len);

	dev_info(dev, "(RX)size: %u\n", rx_desc->rx.size);

	dev_info(dev, "(RX)rss_hash: %u\n", rx_desc->rx.rss_hash);

	dev_info(dev, "(RX)fd_id: %u\n", rx_desc->rx.fd_id);

	dev_info(dev, "(RX)vlan_tag: %u\n", rx_desc->rx.vlan_tag);

	dev_info(dev, "(RX)o_dm_vlan_id_fb: %u\n", rx_desc->rx.o_dm_vlan_id_fb);

	dev_info(dev, "(RX)ot_vlan_tag: %u\n", rx_desc->rx.ot_vlan_tag);

	dev_info(dev, "(RX)bd_base_info: %u\n", rx_desc->rx.bd_base_info);

	dev_info(dev, "(RX)l234_info: %u\n",

		 le32_to_cpu(rx_desc->rx.l234_info));

	dev_info(dev, "(RX)pkt_len: %u\n", le16_to_cpu(rx_desc->rx.pkt_len));

	dev_info(dev, "(RX)size: %u\n", le16_to_cpu(rx_desc->rx.size));

	dev_info(dev, "(RX)rss_hash: %u\n", le32_to_cpu(rx_desc->rx.rss_hash));

	dev_info(dev, "(RX)fd_id: %u\n", le16_to_cpu(rx_desc->rx.fd_id));

	dev_info(dev, "(RX)vlan_tag: %u\n", le16_to_cpu(rx_desc->rx.vlan_tag));

	dev_info(dev, "(RX)o_dm_vlan_id_fb: %u\n",

		 le16_to_cpu(rx_desc->rx.o_dm_vlan_id_fb));

	dev_info(dev, "(RX)ot_vlan_tag: %u\n",

		 le16_to_cpu(rx_desc->rx.ot_vlan_tag));

	dev_info(dev, "(RX)bd_base_info: %u\n",

		 le32_to_cpu(rx_desc->rx.bd_base_info));



	return 0;

}

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+16 −13
Original line number Diff line number Diff line
@@ -1710,8 +1710,8 @@ static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 
	int ret = -EIO;



	netif_dbg(h, drv, netdev,

		  "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=%u\n",

		  vf, vlan, qos, vlan_proto);

		  "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",

		  vf, vlan, qos, ntohs(vlan_proto));



	if (h->ae_algo->ops->set_vf_vlan_filter)

		ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
@@ -1771,7 +1771,7 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 
{

	struct hns3_nic_priv *priv = netdev_priv(ndev);

	struct hnae3_handle *h = hns3_get_handle(ndev);

	struct hns3_enet_ring *tx_ring = NULL;

	struct hns3_enet_ring *tx_ring;

	struct napi_struct *napi;

	int timeout_queue = 0;

	int hw_head, hw_tail;
@@ -1792,6 +1792,9 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 
		    time_after(jiffies,

			       (trans_start + ndev->watchdog_timeo))) {

			timeout_queue = i;

			netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",

				    q->state,

				    jiffies_to_msecs(jiffies - trans_start));

			break;

		}

	}
@@ -1999,7 +2002,7 @@ bool hns3_is_phys_func(struct pci_dev *pdev) 
	case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:

		return false;

	default:

		dev_warn(&pdev->dev, "un-recognized pci device-id %d",

		dev_warn(&pdev->dev, "un-recognized pci device-id %u",

			 dev_id);

	}
@@ -3936,14 +3939,14 @@ static void hns3_info_show(struct hns3_nic_priv *priv) 
	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;



	dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);

	dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);

	dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);

	dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);

	dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);

	dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);

	dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);

	dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);

	dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);

	dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);

	dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);

	dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);

	dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);

	dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);

	dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);

	dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);

	dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);

}



static int hns3_client_init(struct hnae3_handle *handle)
@@ -4563,7 +4566,7 @@ int hns3_set_channels(struct net_device *netdev, 
	if (new_tqp_num > hns3_get_max_available_channels(h) ||

	    new_tqp_num < 1) {

		dev_err(&netdev->dev,

			"Change tqps fail, the tqp range is from 1 to %d",

			"Change tqps fail, the tqp range is from 1 to %u",

			hns3_get_max_available_channels(h));

		return -EINVAL;

	}

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