Commit 2bcefd0d authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds 



Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-6-chris@chris-wilson.co.uk
parent 806a45c0

drivers/gpu/drm/i915/gt/intel_workarounds.c

+22 −5
Original line number Diff line number Diff line
@@ -715,15 +715,28 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) 
}



static void

ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

gen4_gt_workarounds_init(struct drm_i915_private *i915,

			 struct i915_wa_list *wal)

{

	wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);

	/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */

	wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);

}



static void

g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

	gen4_gt_workarounds_init(i915, wal);



	/* WaDisableRenderCachePipelinedFlush:ilk */

	/* WaDisableRenderCachePipelinedFlush:g4x,ilk */

	wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);

}



	/* WaDisable_RenderCache_OperationalFlush:ilk */

	wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);

static void

ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

	g4x_gt_workarounds_init(i915, wal);



	wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);

}



static void
@@ -1209,6 +1222,10 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		snb_gt_workarounds_init(i915, wal);

	else if (IS_GEN(i915, 5))

		ilk_gt_workarounds_init(i915, wal);

	else if (IS_G4X(i915))

		g4x_gt_workarounds_init(i915, wal);

	else if (IS_GEN(i915, 4))

		gen4_gt_workarounds_init(i915, wal);

	else if (INTEL_GEN(i915) <= 8)

		return;

	else

drivers/gpu/drm/i915/intel_pm.c

+0 −15
Original line number Diff line number Diff line
@@ -7399,13 +7399,6 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) 
		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;

	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);



	/* WaDisableRenderCachePipelinedFlush */

	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:g4x */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	g4x_disable_trickle_feed(dev_priv);

}
@@ -7421,11 +7414,6 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv) 
	intel_uncore_write(uncore,

			   MI_ARB_STATE,

			   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:gen4 */

	intel_uncore_write(uncore,

			   CACHE_MODE_0,

			   _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));

}



static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7438,9 +7426,6 @@ static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) 
	I915_WRITE(RENCLK_GATE_D2, 0);

	I915_WRITE(MI_ARB_STATE,

		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:gen4 */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));

}



static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)

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