Commit 2b7cfaaf authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-dt-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt 

i.MX arm32 device tree change for 5.10:

- New board/device support: Tolino Shine 2 HD, TQMa6 SoM, Y Soft IOTA
  Orion board.
- update GPMI NAND node name to nand-controller for aligning with DT
  schema.
- Remove the legacy fsl,spi-num-chipselects property from a few board.
- A series to update imx6q-logicpd support, using GPIO chipselect,
  adding board compatible string, and enabling DTB build for the board.
- Complete RNG device node in i.MX6SL device tree, and add RNG node for
  i.MX6SLL and i.MX6ULL.
- Correct interrupt flags for imx6qdl-gw5xxx boards.
- Add missing enet_out clock for i.MX6Q/DL Ethernet device.
- Enable PCIe support for imx6qp-sabreauto board.
- A series from Shengjiu Wang to add audio sound card for imx7d-sdb and
  imx6sll-evk board, add headphone detection for sound card on a few NXP
  development boards.
- A couple of minor fix-ups on i.MX25 pin functions.
- Some random update on various boards.

* tag 'imx-dt-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (37 commits)
  ARM: dts: imx6qdl-gw5xxx: correct interrupt flags
  ARM: dts: imx6q-logicpd: Use GPIO chipselect
  ARM: dts: imx: Add an entry for imx6q-logicpd.dtb
  ARM: dts: imx6q-logicpd: Add a specific board compatible string
  ARM: dts: imx6q: align GPIO hog names with dtschema
  ARM: dts: imx6qdl-tqma6: fix LM75 compatible string
  ARM: dts: imx6qdl-tqma6: remove obsolete fsl,spi-num-chipselects
  ARM: dts: imx6qdl-tqma6: fix indentation
  ARM: dts: imx28-m28: Align GPMI NAND node name with schema
  ARM: dts: imx6qdl: add enet_out clk support
  ARM: dts: imx6qdl: move iomuxc compatible assignment out of root node
  ARM: dts: vf: Fix PCA95xx GPIO expander properties on ZII CFU1
  ARM: dts: imx: add devicetree for Tolino Shine 2 HD
  ARM: dts: imx6qdl-gw553x: Remove unneeded #address-cells/#size-cells
  ARM: dts: imx6sll-evk: Add audio sound card node
  ARM: dts: imx6sl-evk: Add headphone detection for sound card
  ARM: dts: imx6sx-sdb: Add headphone detection for sound card
  ARM: dts: imx6q-kontron-samx6i: Remove old fsl,spi-num-chipselects
  ARM: dts: imx: Fix the SPI chipselect polarity
  ARM: dts: imx25-pinfunc: Fix GPT function names
  ...

Link: https://lore.kernel.org/r/20200923073009.23678-4-shawnguo@kernel.org


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 53169602 05b0852e

arch/arm/boot/dts/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -484,6 +484,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ 
	imx6dl-wandboard-revd1.dtb \

	imx6dl-yapp4-draco.dtb \

	imx6dl-yapp4-hydra.dtb \

	imx6dl-yapp4-orion.dtb \

	imx6dl-yapp4-ursa.dtb \

	imx6q-apalis-eval.dtb \

	imx6q-apalis-ixora.dtb \
@@ -533,6 +534,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ 
	imx6q-icore-ofcap12.dtb \

	imx6q-icore-rqs.dtb \

	imx6q-kp-tpc.dtb \

	imx6q-logicpd.dtb \

	imx6q-marsboard.dtb \

	imx6q-mccmon6.dtb \

	imx6q-nitrogen6x.dtb \
@@ -587,6 +589,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ 
	imx6qp-zii-rdu2.dtb

dtb-$(CONFIG_SOC_IMX6SL) += \

	imx6sl-evk.dtb \

	imx6sl-tolino-shine2hd.dtb \

	imx6sl-tolino-shine3.dtb \

	imx6sl-warp.dtb

dtb-$(CONFIG_SOC_IMX6SLL) += \

arch/arm/boot/dts/imx23-evk.dts

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 


	apb@80000000 {

		apbh@80000000 {

			gpmi-nand@8000c000 {

			nand-controller@8000c000 {

				pinctrl-names = "default";

				pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;

				status = "okay";

arch/arm/boot/dts/imx23.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ 
				status = "disabled";

			};



			gpmi-nand@8000c000 {

			nand-controller@8000c000 {

				compatible = "fsl,imx23-gpmi-nand";

				#address-cells = <1>;

				#size-cells = <1>;

arch/arm/boot/dts/imx25-pinfunc.h

+22 −6
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ 
#define MX25_PAD_EB1__EB1			0x044 0x25c 0x000 0x00 0x000

#define MX25_PAD_EB1__AUD4_RXD			0x044 0x25c 0x460 0x04 0x000

#define MX25_PAD_EB1__GPIO_2_13			0x044 0x25c 0x000 0x05 0x000

#define MX25_PAD_EB1__CSPI3_SS1			0x044 0x25c 0x4c0 0x06 0x000



#define MX25_PAD_OE__OE				0x048 0x260 0x000 0x00 0x000

#define MX25_PAD_OE__AUD4_TXC			0x048 0x260 0x000 0x04 0x000
@@ -112,6 +113,7 @@ 
#define MX25_PAD_CS5__CSPI3_MISO		0x058 0x268 0x4b4 0x06 0x000



#define MX25_PAD_NF_CE0__NF_CE0			0x05c 0x26c 0x000 0x00 0x000

#define MX25_PAD_NF_CE0__CSPI1_SS3		0x05c 0x26c 0x490 0x01 0x000

#define MX25_PAD_NF_CE0__GPIO_3_22		0x05c 0x26c 0x000 0x05 0x000



#define MX25_PAD_ECB__ECB			0x060 0x270 0x000 0x00 0x000
@@ -122,6 +124,7 @@ 
#define MX25_PAD_LBA__LBA			0x064 0x274 0x000 0x00 0x000

#define MX25_PAD_LBA__UART5_RXD			0x064 0x274 0x578 0x03 0x000

#define MX25_PAD_LBA__GPIO_3_24			0x064 0x274 0x000 0x05 0x000

#define MX25_PAD_LBA__CSPI3_RDY			0x064 0x274 0x4b0 0x06 0x000



#define MX25_PAD_BCLK__BCLK			0x068 0x000 0x000 0x00 0x000

#define MX25_PAD_BCLK__GPIO_4_4			0x068 0x000 0x000 0x05 0x000
@@ -285,7 +288,8 @@ 
#define MX25_PAD_OE_ACD__GPIO_1_25		0x114 0x30c 0x000 0x05 0x000



#define MX25_PAD_CONTRAST__CONTRAST		0x118 0x310 0x000 0x00 0x000

#define MX25_PAD_CONTRAST__CC4			0x118 0x310 0x000 0x01 0x000

#define MX25_PAD_CONTRAST__GPT4_CAPIN1		0x118 0x310 0x000 0x01 0x000

#define MX25_PAD_CONTRAST__CSPI2_SS1		0x118 0x310 0x4a8 0x02 0x000

#define MX25_PAD_CONTRAST__PWM4_PWMO		0x118 0x310 0x000 0x04 0x000

#define MX25_PAD_CONTRAST__FEC_CRS		0x118 0x310 0x508 0x05 0x001

#define MX25_PAD_CONTRAST__USBH2_PWR		0x118 0x310 0x000 0x06 0x000
@@ -298,7 +302,7 @@ 
#define MX25_PAD_CSI_D2__UART5_RXD		0x120 0x318 0x578 0x01 0x001

#define MX25_PAD_CSI_D2__SIM1_CLK0		0x120 0x318 0x000 0x04 0x000

#define MX25_PAD_CSI_D2__GPIO_1_27		0x120 0x318 0x000 0x05 0x000

#define MX25_PAD_CSI_D2__CSPI3_MOSI		0x120 0x318 0x000 0x07 0x000

#define MX25_PAD_CSI_D2__CSPI3_MOSI		0x120 0x318 0x4b8 0x07 0x001



#define MX25_PAD_CSI_D3__CSI_D3			0x124 0x31c 0x000 0x00 0x000

#define MX25_PAD_CSI_D3__UART5_TXD		0x124 0x31c 0x000 0x01 0x000
@@ -310,23 +314,25 @@ 
#define MX25_PAD_CSI_D4__UART5_RTS		0x128 0x320 0x574 0x01 0x001

#define MX25_PAD_CSI_D4__SIM1_VEN0		0x128 0x320 0x000 0x04 0x000

#define MX25_PAD_CSI_D4__GPIO_1_29		0x128 0x320 0x000 0x05 0x000

#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x000 0x07 0x000

#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x4ac 0x07 0x001



#define MX25_PAD_CSI_D5__CSI_D5			0x12c 0x324 0x000 0x00 0x000

#define MX25_PAD_CSI_D5__UART5_CTS		0x12c 0x324 0x000 0x01 0x000

#define MX25_PAD_CSI_D5__SIM1_TX0		0x12c 0x324 0x000 0x04 0x000

#define MX25_PAD_CSI_D5__GPIO_1_30		0x12c 0x324 0x000 0x05 0x000

#define MX25_PAD_CSI_D5__CSPI3_RDY		0x12c 0x324 0x000 0x07 0x000

#define MX25_PAD_CSI_D5__CSPI3_RDY		0x12c 0x324 0x4b0 0x07 0x001



#define MX25_PAD_CSI_D6__CSI_D6			0x130 0x328 0x000 0x00 0x000

/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */

#define MX25_PAD_CSI_D6__ESDHC2_CMD		0x130 0x328 0x4e0 0x12 0x001

#define MX25_PAD_CSI_D6__SIM1_PD0		0x130 0x328 0x000 0x04 0x000

#define MX25_PAD_CSI_D6__GPIO_1_31		0x130 0x328 0x000 0x05 0x000

#define MX25_PAD_CSI_D6__CSPI3_SS0		0x130 0x328 0x4bc 0x07 0x001



#define MX25_PAD_CSI_D7__CSI_D7			0x134 0x32c 0x000 0x00 0x000

#define MX25_PAD_CSI_D7__ESDHC2_CLK		0x134 0x32C 0x4dc 0x02 0x001

#define MX25_PAD_CSI_D7__GPIO_1_6		0x134 0x32c 0x000 0x05 0x000

#define MX25_PAD_CSI_D7__CSPI3_SS1		0x134 0x32c 0x4c0 0x07 0x001



#define MX25_PAD_CSI_D8__CSI_D8			0x138 0x330 0x000 0x00 0x000

#define MX25_PAD_CSI_D8__AUD6_RXC		0x138 0x330 0x000 0x02 0x000
@@ -398,7 +404,7 @@ 


#define MX25_PAD_UART1_RTS__UART1_RTS		0x178 0x370 0x000 0x00 0x000

#define MX25_PAD_UART1_RTS__CSI_D0		0x178 0x370 0x488 0x01 0x001

#define MX25_PAD_UART1_RTS__CC3			0x178 0x370 0x000 0x02 0x000

#define MX25_PAD_UART1_RTS__GPT3_CAPIN1		0x178 0x370 0x000 0x02 0x000

#define MX25_PAD_UART1_RTS__UART2_DCD		0x178 0x370 0x000 0x03 0x000

#define MX25_PAD_UART1_RTS__GPIO_4_24		0x178 0x370 0x000 0x05 0x000
@@ -415,12 +421,14 @@ 


#define MX25_PAD_UART2_RTS__UART2_RTS		0x188 0x380 0x000 0x00 0x000

#define MX25_PAD_UART2_RTS__FEC_COL		0x188 0x380 0x504 0x02 0x002

#define MX25_PAD_UART2_RTS__CC1			0x188 0x380 0x000 0x03 0x000

#define MX25_PAD_UART2_RTS__GPT1_CAPIN1		0x188 0x380 0x000 0x03 0x000

#define MX25_PAD_UART2_RTS__GPIO_4_28		0x188 0x380 0x000 0x05 0x000

#define MX25_PAD_UART2_RTS__CSPI2_SS3		0x188 0x380 0x000 0x06 0x000



#define MX25_PAD_UART2_CTS__UART2_CTS		0x18c 0x384 0x000 0x00 0x000

#define MX25_PAD_UART2_CTS__FEC_RX_ERR		0x18c 0x384 0x518 0x02 0x002

#define MX25_PAD_UART2_CTS__GPIO_4_29		0x18c 0x384 0x000 0x05 0x000

#define MX25_PAD_UART2_CTS__CSPI3_SS3		0x18c 0x384 0x4c8 0x06 0x001



/*

 * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
@@ -446,14 +454,17 @@ 
#define MX25_PAD_SD1_DATA0__GPIO_2_25		0x198 0x390 0x000 0x05 0x000



#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x19c 0x394 0x000 0x00 0x000

#define MX25_PAD_SD1_DATA1__CSPI2_RDY		0x19c 0x394 0x498 0x01 0x001

#define MX25_PAD_SD1_DATA1__AUD7_RXD		0x19c 0x394 0x478 0x03 0x000

#define MX25_PAD_SD1_DATA1__GPIO_2_26		0x19c 0x394 0x000 0x05 0x000



#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x1a0 0x398 0x000 0x00 0x000

#define MX25_PAD_SD1_DATA2__CSPI2_SS0		0x1a0 0x398 0x4a4 0x01 0x001

#define MX25_PAD_SD1_DATA2__FEC_RX_CLK		0x1a0 0x398 0x514 0x02 0x002

#define MX25_PAD_SD1_DATA2__GPIO_2_27		0x1a0 0x398 0x000 0x05 0x000



#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x1a4 0x39c 0x000 0x00 0x000

#define MX25_PAD_SD1_DATA3__CSPI2_SS1		0x1a4 0x39c 0x4a8 0x01 0x001

#define MX25_PAD_SD1_DATA3__FEC_CRS		0x1a4 0x39c 0x508 0x02 0x002

#define MX25_PAD_SD1_DATA3__GPIO_2_28		0x1a4 0x39c 0x000 0x05 0x000
@@ -564,11 +575,15 @@ 
#define MX25_PAD_GPIO_C__PWM4_PWMO		0x1fc 0x3f8 0x000 0x01 0x000

#define MX25_PAD_GPIO_C__I2C2_SCL		0x1fc 0x3f8 0x51c 0x02 0x001

#define MX25_PAD_GPIO_C__KPP_COL4		0x1fc 0x3f8 0x52c 0x03 0x001

#define MX25_PAD_GPIO_C__GPT2_CAPIN1		0x1fc 0x3f8 0x000 0x04 0x000

#define MX25_PAD_GPIO_C__CSPI1_SS2		0x1fc 0x3f8 0x000 0x05 0x000

#define MX25_PAD_GPIO_C__CAN2_TX		0x1fc 0x3f8 0x000 0x06 0x000

#define MX25_PAD_GPIO_C__CSPI2_SS2		0x1fc 0x3f8 0x000 0x07 0x000



#define MX25_PAD_GPIO_D__GPIO_D			0x200 0x3fc 0x000 0x00 0x000

#define MX25_PAD_GPIO_D__I2C2_SDA		0x200 0x3fc 0x520 0x02 0x001

#define MX25_PAD_GPIO_D__CAN2_RX		0x200 0x3fc 0x484 0x06 0x001

#define MX25_PAD_GPIO_D__CSPI3_SS2		0x200 0x3fc 0x4c4 0x07 0x001



#define MX25_PAD_GPIO_E__GPIO_E			0x204 0x400 0x000 0x00 0x000

#define MX25_PAD_GPIO_E__I2C3_CLK		0x204 0x400 0x524 0x01 0x002
@@ -593,6 +608,7 @@ 
#define MX25_PAD_VSTBY_REQ__UART4_RTS		0x214 0x408 0x56c 0x06 0x002



#define MX25_PAD_VSTBY_ACK__VSTBY_ACK		0x218 0x40c 0x000 0x00 0x000

#define MX25_PAD_VSTBY_ACK__CSPI1_SS3		0x218 0x40c 0x490 0x02 0x001

#define MX25_PAD_VSTBY_ACK__GPIO_3_18		0x218 0x40c 0x000 0x05 0x000



#define MX25_PAD_POWER_FAIL__POWER_FAIL		0x21c 0x410 0x000 0x00 0x000

arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -18,8 +18,8 @@ 
};



&cspi1 {

	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,

		   <&gpio4 27 GPIO_ACTIVE_HIGH>;

	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,

		   <&gpio4 27 GPIO_ACTIVE_LOW>;

	status = "okay";

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE