Commit 2b4cebe4 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50: use "nv86" tlb flush method on everything except 0x50/0xac 



It has been reported that this greatly improves (and possibly fixes
completely) the stability of NVA3+ chipsets.  In traces of my NVA8,
NVIDIA now appear to be doing this too.

The most recent traces of 0x50 and 0xac I could find don't show NVIDIA
checking PGRAPH status on these flushes, so for now, we won't either.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c0929b49

drivers/gpu/drm/nouveau/nouveau_drv.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -1190,7 +1190,7 @@ extern int nv50_graph_load_context(struct nouveau_channel *); 
extern int  nv50_graph_unload_context(struct drm_device *);

extern int  nv50_graph_unload_context(struct drm_device *);

extern int  nv50_grctx_init(struct nouveau_grctx *);

extern int  nv50_grctx_init(struct nouveau_grctx *);

extern void nv50_graph_tlb_flush(struct drm_device *dev);

extern void nv50_graph_tlb_flush(struct drm_device *dev);

extern void nv86_graph_tlb_flush(struct drm_device *dev);

extern void nv84_graph_tlb_flush(struct drm_device *dev);

extern struct nouveau_enum nv50_data_error_names[];

extern struct nouveau_enum nv50_data_error_names[];





/* nvc0_graph.c */

/* nvc0_graph.c */

drivers/gpu/drm/nouveau/nouveau_state.c

+4 −8
Original line number Original line Diff line number Diff line
@@ -376,15 +376,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->graph.destroy_context	= nv50_graph_destroy_context;

		engine->graph.destroy_context	= nv50_graph_destroy_context;

		engine->graph.load_context	= nv50_graph_load_context;

		engine->graph.load_context	= nv50_graph_load_context;

		engine->graph.unload_context	= nv50_graph_unload_context;

		engine->graph.unload_context	= nv50_graph_unload_context;

		if (dev_priv->chipset != 0x86)

		if (dev_priv->chipset == 0x50 ||

		    dev_priv->chipset == 0xac)

			engine->graph.tlb_flush	= nv50_graph_tlb_flush;

			engine->graph.tlb_flush	= nv50_graph_tlb_flush;

		else {

		else

			/* from what i can see nvidia do this on every

			engine->graph.tlb_flush	= nv84_graph_tlb_flush;

			 * pre-NVA3 board except NVAC, but, we've only

			 * ever seen problems on NV86

			 */

			engine->graph.tlb_flush	= nv86_graph_tlb_flush;

		}

		engine->fifo.channels		= 128;

		engine->fifo.channels		= 128;

		engine->fifo.init		= nv50_fifo_init;

		engine->fifo.init		= nv50_fifo_init;

		engine->fifo.takedown		= nv50_fifo_takedown;

		engine->fifo.takedown		= nv50_fifo_takedown;

drivers/gpu/drm/nouveau/nv50_graph.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -503,7 +503,7 @@ nv50_graph_tlb_flush(struct drm_device *dev) 
}

}





void

void

nv86_graph_tlb_flush(struct drm_device *dev)

nv84_graph_tlb_flush(struct drm_device *dev)

{

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;

	struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;

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