Commit 2b37e9a2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze 

Pull microblaze update from Michal Simek:
 "Microblaze changes.

  After my discussion with Arnd I have also added there asm-generic io
  patch which is Acked by him and Geert."

* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
  asm-generic: io: Fix ioread16/32be and iowrite16/32be
  microblaze: Do not use module.h in files which are not modules
  microblaze: Fix coding style issues
  microblaze: Add missing return from debugfs_tlb
  microblaze: Makefile clean
  microblaze: Add .gitignore entries for auto-generated files
  microblaze: Fix strncpy_from_user macro
parents a9a07d40 711e5b45

arch/microblaze/Makefile

+3 −6
Original line number Diff line number Diff line
@@ -69,16 +69,13 @@ export MMU DTB 


all: linux.bin



# With make 3.82 we cannot mix normal and wildcard targets

BOOT_TARGETS1 = linux.bin linux.bin.gz

BOOT_TARGETS2 = simpleImage.%



archclean:

	$(Q)$(MAKE) $(clean)=$(boot)



$(BOOT_TARGETS1): vmlinux

linux.bin linux.bin.gz: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@

$(BOOT_TARGETS2): vmlinux



simpleImage.%: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@



define archhelp

arch/microblaze/boot/.gitignore

0 → 100644
+3 −0
Original line number Diff line number Diff line 
*.dtb

linux.bin*

simpleImage.*

arch/microblaze/include/asm/io.h

+1 −1
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ static inline void writel(unsigned int v, volatile void __iomem *addr) 
#define page_to_bus(page)	(page_to_phys(page))

#define bus_to_virt(addr)	(phys_to_virt(addr))



extern void iounmap(void *addr);

extern void iounmap(void __iomem *addr);

/*extern void *__ioremap(phys_addr_t address, unsigned long size,

		unsigned long flags);*/

extern void __iomem *ioremap(phys_addr_t address, unsigned long size);

arch/microblaze/kernel/.gitignore

0 → 100644
+1 −0
Original line number Diff line number Diff line 
vmlinux.lds

arch/microblaze/kernel/cpu/cache.c

+68 −80
Original line number Diff line number Diff line
@@ -17,82 +17,70 @@ 


static inline void __enable_icache_msr(void)

{

	__asm__ __volatile__ ("	msrset	r0, %0;		\

				nop; "			\

	__asm__ __volatile__ ("	 msrset	r0, %0;"	\

				"nop;"			\

			: : "i" (MSR_ICE) : "memory");

}



static inline void __disable_icache_msr(void)

{

	__asm__ __volatile__ ("	msrclr	r0, %0;		\

				nop; "			\

	__asm__ __volatile__ ("	 msrclr	r0, %0;"	\

				"nop;"			\

			: : "i" (MSR_ICE) : "memory");

}



static inline void __enable_dcache_msr(void)

{

	__asm__ __volatile__ ("	msrset	r0, %0;		\

				nop; "			\

				:			\

				: "i" (MSR_DCE)		\

				: "memory");

	__asm__ __volatile__ ("	 msrset	r0, %0;"	\

				"nop;"			\

			: : "i" (MSR_DCE) : "memory");

}



static inline void __disable_dcache_msr(void)

{

	__asm__ __volatile__ ("	msrclr	r0, %0;		\

				nop; "			\

				:			\

				: "i" (MSR_DCE)		\

				: "memory");

	__asm__ __volatile__ ("	 msrclr	r0, %0;"	\

				"nop; "			\

			: : "i" (MSR_DCE) : "memory");

}



static inline void __enable_icache_nomsr(void)

{

	__asm__ __volatile__ ("	mfs	r12, rmsr;	\

				nop;			\

				ori	r12, r12, %0;	\

				mts	rmsr, r12;	\

				nop; "			\

				:			\

				: "i" (MSR_ICE)		\

				: "memory", "r12");

	__asm__ __volatile__ ("	 mfs	r12, rmsr;"	\

				"nop;"			\

				"ori	r12, r12, %0;"	\

				"mts	rmsr, r12;"	\

				"nop;"			\

			: : "i" (MSR_ICE) : "memory", "r12");

}



static inline void __disable_icache_nomsr(void)

{

	__asm__ __volatile__ ("	mfs	r12, rmsr;	\

				nop;			\

				andi	r12, r12, ~%0;	\

				mts	rmsr, r12;	\

				nop; "			\

				:			\

				: "i" (MSR_ICE)		\

				: "memory", "r12");

	__asm__ __volatile__ ("	 mfs	r12, rmsr;"	\

				"nop;"			\

				"andi	r12, r12, ~%0;"	\

				"mts	rmsr, r12;"	\

				"nop;"			\

			: : "i" (MSR_ICE) : "memory", "r12");

}



static inline void __enable_dcache_nomsr(void)

{

	__asm__ __volatile__ ("	mfs	r12, rmsr;	\

				nop;			\

				ori	r12, r12, %0;	\

				mts	rmsr, r12;	\

				nop; "			\

				:			\

				: "i" (MSR_DCE)		\

				: "memory", "r12");

	__asm__ __volatile__ ("	 mfs	r12, rmsr;"	\

				"nop;"			\

				"ori	r12, r12, %0;"	\

				"mts	rmsr, r12;"	\

				"nop;"			\

			: : "i" (MSR_DCE) : "memory", "r12");

}



static inline void __disable_dcache_nomsr(void)

{

	__asm__ __volatile__ ("	mfs	r12, rmsr;	\

				nop;			\

				andi	r12, r12, ~%0;	\

				mts	rmsr, r12;	\

				nop; "			\

				:			\

				: "i" (MSR_DCE)		\

				: "memory", "r12");

	__asm__ __volatile__ ("	 mfs	r12, rmsr;"	\

				"nop;"			\

				"andi	r12, r12, ~%0;"	\

				"mts	rmsr, r12;"	\

				"nop;"			\

			: : "i" (MSR_DCE) : "memory", "r12");

}
@@ -106,7 +94,7 @@ do { \ 
	int align = ~(cache_line_length - 1);				\

	end = min(start + cache_size, end);				\

	start &= align;							\

} while (0);

} while (0)



/*

 * Helper macro to loop over the specified cache_size/line_length and
@@ -118,12 +106,12 @@ do { \ 
	int step = -line_length;					\

	WARN_ON(step >= 0);						\

									\

	__asm__ __volatile__ (" 1:      " #op " %0, r0;			\

					bgtid   %0, 1b;			\

					addk    %0, %0, %1;		\

					" : : "r" (len), "r" (step)	\

	__asm__ __volatile__ (" 1:      " #op " %0, r0;"		\

					"bgtid   %0, 1b;"		\

					"addk    %0, %0, %1;"		\

					: : "r" (len), "r" (step)	\

					: "memory");			\

} while (0);

} while (0)



/* Used for wdc.flush/clear which can use rB for offset which is not possible

 * to use for simple wdc or wic.
@@ -142,12 +130,12 @@ do { \ 
	count = end - start;						\

	WARN_ON(count < 0);						\

									\

	__asm__ __volatile__ (" 1:	" #op "	%0, %1;			\

					bgtid	%1, 1b;			\

					addk	%1, %1, %2;		\

					" : : "r" (start), "r" (count),	\

	__asm__ __volatile__ (" 1:	" #op "	%0, %1;"		\

					"bgtid	%1, 1b;"		\

					"addk	%1, %1, %2;"		\

					: : "r" (start), "r" (count),	\

					"r" (step) : "memory");		\

} while (0);

} while (0)



/* It is used only first parameter for OP - for wic, wdc */

#define CACHE_RANGE_LOOP_1(start, end, line_length, op)			\
@@ -157,13 +145,13 @@ do { \ 
	end = ((end & align) == end) ? end - line_length : end & align;	\

	WARN_ON(end - start < 0);					\

									\

	__asm__ __volatile__ (" 1:	" #op "	%1, r0;			\

					cmpu	%0, %1, %2;		\

					bgtid	%0, 1b;			\

					addk	%1, %1, %3;		\

				" : : "r" (temp), "r" (start), "r" (end),\

	__asm__ __volatile__ (" 1:	" #op "	%1, r0;"		\

					"cmpu	%0, %1, %2;"		\

					"bgtid	%0, 1b;"		\

					"addk	%1, %1, %3;"		\

				: : "r" (temp), "r" (start), "r" (end),	\

					"r" (line_length) : "memory");	\

} while (0);

} while (0)



#define ASM_LOOP
@@ -352,7 +340,7 @@ static void __invalidate_dcache_all_noirq_wt(void) 
#endif

	pr_debug("%s\n", __func__);

#ifdef ASM_LOOP

	CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc)

	CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);

#else

	for (i = 0; i < cpuinfo.dcache_size;

		 i += cpuinfo.dcache_line_length)
@@ -361,7 +349,8 @@ static void __invalidate_dcache_all_noirq_wt(void) 
#endif

}



/* FIXME It is blindly invalidation as is expected

/*

 * FIXME It is blindly invalidation as is expected

 * but can't be called on noMMU in microblaze_cache_init below

 *

 * MS: noMMU kernel won't boot if simple wdc is used
@@ -375,7 +364,7 @@ static void __invalidate_dcache_all_wb(void) 
	pr_debug("%s\n", __func__);

#ifdef ASM_LOOP

	CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,

					wdc)

					wdc);

#else

	for (i = 0; i < cpuinfo.dcache_size;

		 i += cpuinfo.dcache_line_length)
@@ -616,46 +605,45 @@ static const struct scache wt_nomsr_noirq = { 
#define CPUVER_7_20_A	0x0c

#define CPUVER_7_20_D	0x0f



#define INFO(s)	printk(KERN_INFO "cache: " s "\n");



void microblaze_cache_init(void)

{

	if (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) {

		if (cpuinfo.dcache_wb) {

			INFO("wb_msr");

			pr_info("wb_msr\n");

			mbc = (struct scache *)&wb_msr;

			if (cpuinfo.ver_code <= CPUVER_7_20_D) {

				/* MS: problem with signal handling - hw bug */

				INFO("WB won't work properly");

				pr_info("WB won't work properly\n");

			}

		} else {

			if (cpuinfo.ver_code >= CPUVER_7_20_A) {

				INFO("wt_msr_noirq");

				pr_info("wt_msr_noirq\n");

				mbc = (struct scache *)&wt_msr_noirq;

			} else {

				INFO("wt_msr");

				pr_info("wt_msr\n");

				mbc = (struct scache *)&wt_msr;

			}

		}

	} else {

		if (cpuinfo.dcache_wb) {

			INFO("wb_nomsr");

			pr_info("wb_nomsr\n");

			mbc = (struct scache *)&wb_nomsr;

			if (cpuinfo.ver_code <= CPUVER_7_20_D) {

				/* MS: problem with signal handling - hw bug */

				INFO("WB won't work properly");

				pr_info("WB won't work properly\n");

			}

		} else {

			if (cpuinfo.ver_code >= CPUVER_7_20_A) {

				INFO("wt_nomsr_noirq");

				pr_info("wt_nomsr_noirq\n");

				mbc = (struct scache *)&wt_nomsr_noirq;

			} else {

				INFO("wt_nomsr");

				pr_info("wt_nomsr\n");

				mbc = (struct scache *)&wt_nomsr;

			}

		}

	}

/* FIXME Invalidation is done in U-BOOT

	/*

	 * FIXME Invalidation is done in U-BOOT

	 * WT cache: Data is already written to main memory

	 * WB cache: Discard data on noMMU which caused that kernel doesn't boot

	 */

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