Commit 2b1202d7 authored by Tero Kristo's avatar Tero Kristo Committed by Stephen Boyd
Browse files

clk: ti: dra7x: prevent non-existing clkctrl clocks from registering 



Certain clkctrl clocks (like the USB_OTG_SS4) do not exist on some
variants of the dra7x SoC. Append a flag for these clocks and skip
the registration in cases where the clocks do not exist.

Reported-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a348f053

drivers/clk/ti/clk-7xx-compat.c

+1 −1
Original line number Diff line number Diff line
@@ -362,7 +362,7 @@ static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst 
	{ DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },

	{ DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },

	{ DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },

	{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },

	{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },

	{ DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },

	{ DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },

	{ DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },

drivers/clk/ti/clk-7xx.c

+1 −1
Original line number Diff line number Diff line
@@ -348,7 +348,7 @@ static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst 
	{ DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },

	{ DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },

	{ DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },

	{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },

	{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },

	{ DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },

	{ DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },

	{ DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },

drivers/clk/ti/clkctrl.c

+14 −0
Original line number Diff line number Diff line
@@ -446,6 +446,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) 
	u32 addr;

	int ret;

	char *c;

	u16 soc_mask = 0;



	if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&

	    of_node_name_eq(node, "clk"))
@@ -469,6 +470,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) 
		else

			data = dra7_clkctrl_data;

	}



	if (of_machine_is_compatible("ti,dra72"))

		soc_mask = CLKF_SOC_DRA72;

	if (of_machine_is_compatible("ti,dra74"))

		soc_mask = CLKF_SOC_DRA74;

	if (of_machine_is_compatible("ti,dra76"))

		soc_mask = CLKF_SOC_DRA76;

#endif

#ifdef CONFIG_SOC_AM33XX

	if (of_machine_is_compatible("ti,am33xx")) {
@@ -562,6 +570,12 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) 
	reg_data = data->regs;



	while (reg_data->parent) {

		if ((reg_data->flags & CLKF_SOC_MASK) &&

		    (reg_data->flags & soc_mask) == 0) {

			reg_data++;

			continue;

		}



		hw = kzalloc(sizeof(*hw), GFP_KERNEL);

		if (!hw)

			return;

drivers/clk/ti/clock.h

+6 −0
Original line number Diff line number Diff line
@@ -83,6 +83,12 @@ enum { 
#define CLKF_HW_SUP			BIT(6)

#define CLKF_NO_IDLEST			BIT(7)



#define CLKF_SOC_MASK			GENMASK(10, 8)



#define CLKF_SOC_DRA72			BIT(8)

#define CLKF_SOC_DRA74			BIT(9)

#define CLKF_SOC_DRA76			BIT(10)



#define CLK(dev, con, ck)		\

	{				\

		.lk = {			\

CRA Git | Maintained and supported by SUSTech CRA and CCSE