arm64: dts: msm8996: Add proper capacity scaling for the cpus (2aefca80) · Commits · 戴 / test

msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Add capacity-dmips-mhz property to allow the topology code to determine the actual capacity by taking into account the highest frequency for each CPU. Acked-by:

Daniel Lezcano <daniel.lezcano@linaro.org> Suggested-by:

Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:

Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by:

Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:

Andy Gross <agross@kernel.org>

arch/arm64/boot/dts/qcom/msm8996.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -103,6 +103,7 @@
		reg = <0x0 0x0>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		next-level-cache = <&L2_0>;
		L2_0: l2-cache {
		compatible = "cache";
		@@ -116,6 +117,7 @@
		reg = <0x0 0x1>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		next-level-cache = <&L2_0>;
		};

		@@ -125,6 +127,7 @@
		reg = <0x0 0x100>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		next-level-cache = <&L2_1>;
		L2_1: l2-cache {
		compatible = "cache";
		@@ -138,6 +141,7 @@
		reg = <0x0 0x101>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		next-level-cache = <&L2_1>;
		};

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